Charge Transfer Device Patents (Class 257/183.1)
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Patent number: 10522583Abstract: A photoelectric conversion element and an optical sensor including the same are disclosed. The photoelectric conversion element may include a plurality of lattice stacks repeatedly stacked on top of each other on a substrate and configured to have an effective band gap. The plurality of lattice stacks may each include a first active layer and a second active layer on the first active layer. The first active layer may include a first two-dimensional material having a first band gap. The second active layer may include a second two-dimensional material having a second band gap not overlapping the first band gap. An effective band gap may be adjusted based on the first two-dimensional materials and thicknesses of the first active layer and the second active layer and a number of times of plurality of lattice stacks.Type: GrantFiled: February 15, 2018Date of Patent: December 31, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Haeryong Kim, Jaeho Lee, Sanghyun Jo, Hyeonjin Shin
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Patent number: 9691940Abstract: A nitride semiconductor structure including a substrate, a cap layer, a nucleation layer, a transition layer and a composite buffer structure is provided. The cap layer is located on the substrate. The nucleation layer is located between the substrate and the cap layer. The transition layer is located between the nucleation layer and the cap layer, wherein the transition layer is an AlxGaN layer. The composite buffer structure is located between the transition layer and the cap layer. The composite buffer structure includes a first composite buffer layer, wherein the first composite buffer layer includes a plurality of first AlyGaN layers and a plurality of first GaN layers alternately stacking with each other, and the x is equal to the y.Type: GrantFiled: May 6, 2016Date of Patent: June 27, 2017Assignee: Episil-Precision Inc.Inventors: Chih-Wei Hu, Jin-Ji Dai, Jung Hsuan
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Patent number: 9385321Abstract: A real-space charge-transfer device is disclosed. In particular, a Gunn diode is disclosed having a conductive structure fabricated overlying its active region. A secondary signal, other than the normal Gunn diode signal, is generated by the Gunn diode based upon a characteristic of the overlying conductive structure. For example, when the conductive structure is a grate having N teeth the secondary signal will have N secondary oscillation cycles that occur during the duration of a single normal Gunn diode oscillation cycle.Type: GrantFiled: December 17, 2014Date of Patent: July 5, 2016Assignee: Freescale Semiconductor, Inc.Inventor: Don D. Smith
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Patent number: 9226383Abstract: A circuit substrate has one or more active components and a plurality of passive circuit elements on a first surface. An active semiconductor device has a substrate with layers of material and a plurality of terminals. The active semiconductor device is flip-chip mounted on the circuit substrate and at least one of the terminals of the device is electrically connected to an active component on the circuit substrate. The active components on the substrate and the flip-chip mounted active semiconductor device, in combination with passive circuit elements, form preamplifiers and an output amplifier respectively. In a power switching configuration, the circuit substrate has logic control circuits on a first surface. A semiconductor transistor flip-chip mounted on the circuit substrate is electrically connected to the control circuits on the first surface to thereby control the on and off switching of the flip-chip mounted device.Type: GrantFiled: July 23, 2014Date of Patent: December 29, 2015Assignee: CREE, INC.Inventors: Umesh Mishra, Primit Parikh, Yifeng Wu
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Patent number: 9142637Abstract: III-nitride materials are used to form isolation structures in high voltage ICs to isolate low voltage and high voltage functions on a monolithic power IC. Critical performance parameters are improved using III-nitride materials, due to the improved breakdown performance and thermal performance available in III-nitride semiconductor materials. An isolation structure may include a dielectric layer that is epitaxially grown using a III-nitride material to provide a simplified manufacturing process. The process permits the use of planar manufacturing technology to avoid additional manufacturing costs. High voltage power ICs have improved performance in a smaller package in comparison to corresponding silicon structures.Type: GrantFiled: February 15, 2011Date of Patent: September 22, 2015Assignee: International Rectifier CorporationInventors: Robert Beach, Paul Bridger
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Patent number: 8963063Abstract: A pixel array including circuitry for combining charges accumulated by individual pixels in the array enables addition and/or subtraction of individual pixel values, prior to their digitization, in the pixel array.Type: GrantFiled: May 3, 2011Date of Patent: February 24, 2015Assignee: The Charles Stark Draper Laboratory, Inc.Inventors: Robin M. A. Dawson, Steven Hoeschele, Juha-Pekka J. Laine, Benjamin F. Lane, Yaron Rachlin, Christopher C. Yu
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Publication number: 20150008482Abstract: According to the embodiments, a semiconductor device having a CMOS image sensor is provided. The CMOS image sensor includes a plurality of photoelectric conversion units adapted to photoelectrically convert an incident light into signal charges; and a transfer unit adapted to transfer the signal charges generated by the photoelectric conversion unit to a floating diffusion unit from the photoelectric conversion unit. A channel portion of a transfer gate transistor of the transfer unit has at least one SiGe layer.Type: ApplicationFiled: February 12, 2014Publication date: January 8, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Motoyuki SATO
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Publication number: 20140312385Abstract: The present invention relates to a device including a ferroic material having a ferroelectric order parameter and including at least two domains, as well as a first and second electrode in electrical contact with the ferroic material. The device is configured to form a head-to-head polarization orientation or a tail-to-tail polarization orientation at an interface between the two domains to form a charged domain wall at said interface and between the first and second electrodes. The present invention relates to a corresponding method for operating such a device.Type: ApplicationFiled: April 18, 2014Publication date: October 23, 2014Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: Tomas SLUKA, Alexander TAGANTSEV
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Patent number: 8860083Abstract: A low noise infrared photodetector has an epitaxial heterostructure that includes a photodiode and a transistor. The photodiode includes a high sensitivity narrow bandgap photodetector layer of first conductivity type, and a collection well of second conductivity type in contact with the photodetector layer. The transistor includes the collection well, a transfer well of second conductivity type that is spaced from the collection well and the photodetector layer, and a region of first conductivity type between the collection and transfer wells.Type: GrantFiled: May 13, 2013Date of Patent: October 14, 2014Assignee: Sensors Unlimited, Inc.Inventor: John Alfred Trezza
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Patent number: 8759884Abstract: An electronic device comprises a functional stack (10) and a cover (50) coupled thereto by an insulating adhesive layer (30). The functional stack (10) comprises a first transparent and electrically conductive layer (22), a second electrically conductive layer (24) and a functional structure (26), comprising at least one layer, sandwiched between said first and second conductive layer. The cover (50) includes a substrate (52) and at least a first conductive structure (66, 68) that is arranged in a first plane between the adhesive layer (28) and the substrate (52). First and second transverse electrical conductors (32, 34) transverse to the first plane (61) electrically interconnect the first and the second electrically conductive layer (22, 24) with the first and the second conductive structure (66, 68) in the first plane (61).Type: GrantFiled: July 7, 2009Date of Patent: June 24, 2014Assignees: Nederlandse Organisatie voor toegepast—natuurwetenschappelijk onderzoek TNO, Koninklijke Philips Electronics N.V.Inventors: Jeroen van den Brand, Andreas Heinrich Dietzel, Edward Willem Albert Young, Herbert Lifka, Erik Dekempeneer
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Patent number: 8749686Abstract: In various embodiments, image sensors include photosensitive pixels, associated vertical CCDs, sense nodes each accepting charge from one or more of the vertical CCDs, and readout circuitry accepting signals from the sense nodes.Type: GrantFiled: April 27, 2012Date of Patent: June 10, 2014Assignee: Truesense Imaging, Inc.Inventor: Edward T. Nelson
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Patent number: 8592243Abstract: A method for forming a buffer layer in a dye-sensitized solar cell including a transparent electrode, a counter electrode, an electrolyte layer disposed between the electrodes, and a photocatalyst film disposed between the electrodes and near the transparent electrode, the buffer layer being disposed between the transparent electrode and photocatalyst film, the method including: forming the buffer layer by sintering a mixed solution of an alcohol solution and 0.03% to 5% by mass of metal alkoxide by laser beam irradiation after applying the mixed solution to the surface of the transparent electrode by spin coating, the transparent electrode being rotated by a rotating table.Type: GrantFiled: December 22, 2010Date of Patent: November 26, 2013Assignee: Hitachi Zosen CorporationInventors: Takeshi Sugiyo, Tetsuya Inoue
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Patent number: 8264013Abstract: A device separation insulating film and a device separation semiconductor layer are provided for a device separation section for separating adjacent devices from each other, end portions of the device separation insulating film and end portions of the device separation semiconductor layer are provided to overlap each other in order to surround two sides of an outer-periphery of the voltage conversion section and also to surround a channel section of the charge transfer device and the light receiving devices and an end portion of the device separation insulating film facing an end face of the light receiving device is arranged inwardly below a control electrode with respect to an end face of the control electrode on the light receiving device side.Type: GrantFiled: February 14, 2008Date of Patent: September 11, 2012Assignee: Sharp Kabushiki KaishaInventor: Tomohiko Kawamura
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Patent number: 7968865Abstract: A heterostructure having a heterojunction comprising: a diamond layer; and a boron aluminum nitride (B(x)Al(1-x)N) layer disposed in contact with a surface of the diamond layer, where x is between 0 and 1.Type: GrantFiled: July 6, 2009Date of Patent: June 28, 2011Assignee: Raytheon CompanyInventors: Jeffrey R. LaRoche, William E. Hoke, Steven D. Bernstein, Ralph Korenstein
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Patent number: 7948534Abstract: A CCD image sensor comprises photosensitive elements arranged in rows and columns, vertical CCDs each having vertical shift elements associated with respective ones of the photosensitive elements of a corresponding one of the columns, and a horizontal CCD comprising horizontal shift elements. The image sensor further comprises a transition region arranged between the vertical CCDs and the horizontal CCD. The transition region is configured to separate each of a plurality of signal channels provided by respective ones of the vertical CCDs into first and second parallel signal channels and to controllably direct selected ones of the parallel signal channels to the horizontal shift elements of the horizontal CCD in accordance with a designated readout sequence.Type: GrantFiled: October 22, 2008Date of Patent: May 24, 2011Assignee: Eastman Kodak CompanyInventor: Eric J. Meisenzahl
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Patent number: 7920198Abstract: A method of transferring charge from a photosensitive array using a plurality of vertical shift registers, each having a plurality of vertical elements including first and last vertical element is disclosed The vertical shift registers are capable of transferring charge in a first direction from the first to the last vertical element The method also includes using at least one horizontal shift register having a plurality of horizontal elements. Each of the horizontal elements is arranged to receive charge transferred from the last vertical element of a respective one of the plurality of vertical shift registers, and shift the charge in a horizontal direction. The method includes operating the horizontal shift register during a plurality of horizontal operating intervals and operating the plurality of vertical shift registers during at least a portion of the plurality of horizontal operating intervals.Type: GrantFiled: August 1, 2008Date of Patent: April 5, 2011Assignee: Analog Devices, Inc.Inventors: David P. Foley, Eitake Ibaragi
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Patent number: 7902574Abstract: This invention provides a type of solid-state image pickup device characterized by the fact that for a solid-state image pickup device with a broad dynamic range, it is possible to suppress the dark current than photoelectrons overflowing from the photodiode, as well as its driving method. Plural pixels are integrated in an array configuration on a semiconductor substrate. Each pixel has the following parts: photodiode (CPD), transfer transistor (?T), floating diffusion (CFD), accumulating capacitive element (CS), accumulating transistor (?S), and a reset transistor. During the accumulating period of photoelectric charge, voltage (?) over that applied on the semiconductor substrate, or ?0.6 V or lower than the voltage applied on the semiconductor substrate, is applied as an OFF potential on the gate electrode of at least one transfer transistor, the accumulating transistor and the reset transistor.Type: GrantFiled: May 16, 2007Date of Patent: March 8, 2011Assignee: Texas Instruments IncorporatedInventor: Satoru Adachi
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Patent number: 7888161Abstract: A method for producing a solid-state imaging device, which including: a photoelectric conversion section; a charge transfer section having a charge transfer electrode; and an antireflection film covering a light-receiving region in the photoelectric conversion section, wherein forming the antireflection film includes: forming a sidewall on a lateral wall of the charge transfer electrode after forming the charge transfer electrode; forming an antireflection film on a substrate surface where the sidewall is formed; forming a resist on the antireflection film; melting and flattening the resist to expose the antireflection film on the charge transfer electrode; removing the antireflection film by using the resist as the mask; removing the sidewall; covering the charge transfer electrode with an insulating film; and forming a light-shielding film that reaches a level lower than the top surface of the antireflection film, and that surrounds the periphery of the antireflection film.Type: GrantFiled: April 24, 2009Date of Patent: February 15, 2011Assignee: Fujifilm CorporationInventor: Takanori Sato
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Patent number: 7851822Abstract: A charge-coupled device includes a photosensitive region for collecting charge in response to incident light; a first and third gate electrode made of a transmissive material spanning at least a portion of the photosensitive region; and a second gate electrode made of a transmissive material that is less transmissive than the first and third gates and spans at least a portion of the photosensitive region; wherein the first, second and third gates are arranged symmetrically within an area that spans the photosensitive region.Type: GrantFiled: June 27, 2006Date of Patent: December 14, 2010Assignee: Eastman Kodak CompanyInventor: Eric J. Meisenzahl
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Patent number: 7842591Abstract: A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.Type: GrantFiled: May 15, 2008Date of Patent: November 30, 2010Assignee: WIN Semiconductors Corp.Inventors: Cheng-Kuo Lin, Chia-Liang Chao, Ming-Chang Tu, Tsung-Chi Tsai, Yu-Chi Wang
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Patent number: 7804149Abstract: The present invention provides methods of forming metal oxide semiconductor nanostructures and, in particular, zinc oxide (ZnO) semiconductor nanostructures, possessing high surface area, plant-like morphologies on a variety of substrates. Optoelectronic devices, such as photovoltaic cells, incorporating the nanostructures are also provided.Type: GrantFiled: April 2, 2007Date of Patent: September 28, 2010Assignee: The University of Utah Research FoundationInventors: Ashutosh Tiwari, Michael R. Snure
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Patent number: 7781801Abstract: An apparatus includes a field-effect transistor (FET). The FET includes a region of first semiconductor and a layer of second semiconductor that is located on the region of the first semiconductor. The layer and region form a semiconductor heterostructure. The FET also includes source and drain electrodes that are located on one of the region and the layer and a gate electrode located to control a conductivity of a channel portion of the semiconductor heterostructure. The channel portion is located between the source and drain electrodes. The gate electrode is located vertically over the channel portion and portions of the source and drain electrodes.Type: GrantFiled: September 25, 2006Date of Patent: August 24, 2010Assignee: Alcatel-Lucent USA Inc.Inventor: Robert L Willett
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Patent number: 7760261Abstract: A solid-state imaging device is provided and includes: a semiconductor substrate having a two-dimensional array of photoelectric conversion elements, each storing a signal charge in accordance with a received amount of light; a charge transfer path that transfers the signal charge read out of the photoelectric conversion elements toward an output end of the solid-state imaging device; and a branching part having two branches, the branching part receiving the signal charge transferred along the charge transfer path and distributing the signal charge toward one of the two branches alternately. The charge transfer path has an end portion narrowed in channel width and connected to the branching part.Type: GrantFiled: February 23, 2007Date of Patent: July 20, 2010Assignee: Fujifilm CorporationInventor: Makoto Kobayashi
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Patent number: 7675076Abstract: A light-emitting device has a main semiconductor region formed via an n-type AlInGaN buffer region on a p-type silicon substrate, the latter being sufficiently electroconductive to provide part of the current path through the device. Constituting the primary working part of the LED, the main semiconductor region comprises an n-type GaN layer, an active layer, and a p-type GaN layer, which are successively epitaxially grown in that order on the buffer region. A heterojunction is created between p-type substrate and n-type buffer region. Carrier transportation from substrate to buffer region is expedited by the interface levels of the heterojunction, with a consequent reduction of the drive voltage requirement of the LED.Type: GrantFiled: March 15, 2006Date of Patent: March 9, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Koji Otsuka, Tetsuji Moku, Junji Sato, Yoshiki Tada, Takashi Yoshida
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Patent number: 7671375Abstract: A light-emitting diode is built on a silicon substrate which has been doped with a p-type impurity to possess sufficient conductivity to provide part of the current path through the LED. The p-type silicon substrate has epitaxially grown thereon a buffer region of n-type AlInGaN. Further grown epitaxially on the buffer region is the main semiconductor region of the LED which comprises a lower confining layer of n-type GaN, an active layer for generating light, and an upper confining layer of p-type GaN. In the course of the growth of the buffer region and main semiconductor region there occurs a thermal diffusion of gallium and other Group III elements from the buffer region into the p-type silicon substrate, with the consequent creation of a p-type low-resistance region in the substrate. Interface levels are created across the heterojunction between p-type silicon substrate and n-type buffer region.Type: GrantFiled: March 17, 2006Date of Patent: March 2, 2010Assignee: Sanken Electric Co., Ltd.Inventors: Koji Otsuka, Tetsuji Moku, Junji Sato, Yoshiki Tada, Takashi Yoshida
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Patent number: 7456442Abstract: The invention provides a device having a substrate, a buffer region positioned upon the substrate, wherein the buffer region has an upper buffer region and a lower buffer region, a heterojunction region positioned upon the buffer region, and a superlattice positioned between the lower buffer region and the upper buffer region, wherein the device is configured to function as a heterojunction field effect transistor.Type: GrantFiled: June 8, 2006Date of Patent: November 25, 2008Assignee: International Rectifier CorporationInventor: Gordon Munns
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Patent number: 7446349Abstract: A two-branch outputting solid-state imaging device is provided and includes: two output amplifiers including a first output amplifier and a second output amplifier, each outputting a voltage signal in accordance with the signal charge transferred toward the output end through the charge transfer path; and a branching part that distributes the signal charge transferred through the charge transfer path toward the first output amplifier in a case the signal charge corresponds to the first signal charge, toward the second output amplifier in a case the signal charge corresponds to the second signal charge, and toward the first output amplifier in a case the signal charge corresponds to the third signal charge.Type: GrantFiled: February 15, 2007Date of Patent: November 4, 2008Assignee: FUJIFILM CorporationInventors: Makoto Kobayashi, Katsumi Ikeda
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Patent number: 7432539Abstract: An improved imaging array (and corresponding method of operation) includes a plurality of heterojunction thyristor-based pixel elements disposed within resonant cavities formed on a substrate. Each thyristor-based pixel element includes complementary n-type and p-type modulation doped quantum well interfaces that are spaced apart from one another. Incident radiation within a predetermined wavelength resonates within the cavity of a given pixel element for absorption therein that causes charge accumulation. The accumulated charge is related to the intensity of the incident radiation. The heterojunction-thyristor-based pixel element is suitable for many imaging applications, including CCD-based imaging arrays and active-pixel imaging arrays.Type: GrantFiled: July 20, 2007Date of Patent: October 7, 2008Assignees: The University of Connecticut, Opel, Inc.Inventor: Geoff W. Taylor
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Patent number: 7342169Abstract: A thermoelectric structure and device including at least first and second material systems having different lattice constants and interposed in contact with each other, and a physical interface at which the at least first and second material systems are joined with a lattice mismatch and at which structural integrity of the first and second material systems is substantially maintained. The at least first and second material systems have a charge carrier transport direction normal to the physical interface and preferably periodically arranged in a superlattice structure.Type: GrantFiled: October 7, 2002Date of Patent: March 11, 2008Assignee: Nextreme Thermal SolutionsInventors: Rama Venkatasubramanian, Edward Siivola, Thomas Colpitts, Brooks O'Quinn
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Patent number: 7317214Abstract: An amplifying solid-state image pickup device includes photoelectric conversion transfer parts respectively composed of a photodiode and a transfer transistor, and a switched capacitor amplification part provided for every k (k: natural number) photoelectric conversion transfer parts. The switched capacitor amplification part includes an inverting amplifier composed of transistors, a reset transistor and a capacitor respectively inserted between input and output of the inverting amplifier, and a select transistor inserted between output side of the inverting amplifier and a vertical signal line. Input side of the inverting amplifier of the switched capacitor amplification part serves as a signal charge storage part common to k photoelectric conversion transfer parts. Output side of the inverting amplifier of the switched capacitor amplification part is connected to the vertical signal line via the select transistor.Type: GrantFiled: December 2, 2004Date of Patent: January 8, 2008Assignee: Sharp Kabushiki KaishaInventor: Takashi Watanabe
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Patent number: 7112830Abstract: The invention provides a device having a substrate, a buffer region positioned upon the substrate, wherein the buffer region has an upper buffer region and a lower buffer region, a heterojunction region positioned upon the buffer region, and a superlattice positioned between the lower buffer region and the upper buffer region, wherein the device is configured to function as a heterojunction field effect transistor.Type: GrantFiled: November 25, 2003Date of Patent: September 26, 2006Assignee: APA Enterprises, Inc.Inventor: Gordon Munns
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Patent number: 7054192Abstract: A method of two-sided asymmetric programming with a one-sided read for a Nitride Read Only Memory (NROM) cell with different quantity of stored charges uses the different interaction of the two bits to control the operation window of the threshold voltage. Due to the increase of the threshold voltage operation window of a NROM cell, four, eight, and sixteen memory states of a NROM cell can be achieved through the combination of the left bit, the right bit, the quantity of charge, and the charge position of its two bits.Type: GrantFiled: February 26, 2004Date of Patent: May 30, 2006Assignee: Macronix International Co., Ltd.Inventor: Chao I. Wu
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Patent number: 6992341Abstract: There is provided an amplifying solid-state image pickup device capable of improving S/N and maintaining a charge-voltage conversion efficiency high. In the amplifying solid-state image pickup device, signal charges of a plurality of photodiodes 1 are added up on an input side of a switched capacitor amplification part 20 via the transfer transistors 2.Type: GrantFiled: February 25, 2005Date of Patent: January 31, 2006Assignee: Sharp Kabuishiki KaishaInventor: Takashi Watanabe
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Patent number: 6933181Abstract: In a method for fabricating a semiconductor device, a first semiconductor layer of aluminum gallium nitride is first formed on a substrate, and a protection film containing silicon is then formed on the first semiconductor layer in such a manner that a device-isolation region is uncovered. Thereafter, the method further includes the step of heat-treating the first semiconductor layer in an oxidizing atmosphere whose temperature is adjusted to be within a range of 950° C. or more and 1050° C. or less.Type: GrantFiled: July 17, 2003Date of Patent: August 23, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kaoru Inoue, Yoshito Ikeda, Katsunori Nishii, Yutaka Hirose
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Patent number: 6929987Abstract: In a method of forming a semiconductor device with a first channel layer formed over a portion of a second channel layer, a portion of the second channel underlying the first channel is etched so as to form an overhanging ledge in the first channel, and then a metallic contact disposed on top of the ledge portion is diffused into the first channel by ohmic alloying to form an electrode in the first channel.Type: GrantFiled: December 23, 2003Date of Patent: August 16, 2005Assignee: HRL Laboratories, LLCInventor: Jeong-Sun Moon
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Patent number: 6917061Abstract: A heterojunction bipolar transistor is provided that has a reduced turn-on voltage threshold. A base spacer layer is provided and alternately an emitter layer is provided that has a lowered energy gap. The lowered energy gap of the base spacer or the emitter spacer allow the heterojunction bipolar transistor to realize a lower turn-on voltage threshold. The thickness of the emitter layer if utilized is kept to a minimum to reduce the associated space charge recombination current in the heterojunction bipolar transistor.Type: GrantFiled: July 22, 2002Date of Patent: July 12, 2005Assignee: Microlink Devices, Inc.Inventors: Noren Pan, Byung-Kwon Han
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Patent number: 6870207Abstract: A photon detector is obtained by using the intersubband absorption mechanism in a modulation doped quantum well(s). The modulation doping creates a very high electric field in the well which enables absorption of input TE polarized light and also conducts the carriers emitted from the well into the modulation doped layer from where they may recombine with carriers from the gate contact. Carriers are resupplied to the well by the generation of electrons across the energy gap of the quantum well material. The absorption is enhanced by the use of a resonant cavity in which the quantum well(s) are placed. The absorption and emission from the well creates a deficiency of charge in the quantum well proportional to the intensity of the input photon signal. The quantity of charge in the quantum well of each detector is converted to an output voltage by transferring the charge to the gate of an output amplifier.Type: GrantFiled: April 24, 2000Date of Patent: March 22, 2005Assignee: The University of ConnecticutInventor: Geoff W Taylor
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Patent number: 6828601Abstract: To transfer signal charges at high speed with small noise, there is provided a charge transfer apparatus including a semiconductor substrate of one conductivity type, a charge transfer region of a conductivity type opposite to that of the semiconductor substrate that is formed in the semiconductor substrate and joined to the semiconductor substrate to form a diode, a signal charge input portion which inputs a signal charge to the charge transfer region, a signal charge output portion which accumulates the signal charge transferred from the charge transfer region, and a plurality of independent potential supply terminals which supply a potential gradient to the semiconductor substrate, wherein the signal charge in the charge transfer region is transferred by the potential gradient formed by the plurality of potential supply terminals.Type: GrantFiled: June 7, 2001Date of Patent: December 7, 2004Assignee: Canon Kabushiki KaishaInventor: Mahito Shinohara
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Patent number: 6670657Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.Type: GrantFiled: January 11, 2002Date of Patent: December 30, 2003Assignee: STMicroelectronics S.A.Inventors: Olivier Menut, Yvon Gris
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Patent number: 6566694Abstract: A heterojunction bipolar transferred electron tetrode has an anode region providing a first terminal, an active region in which Gunn-Hilsum oscillations are generated, a base region providing a second terminal, a cathode region providing a third terminal, and a fourth terminal which is operable independently of the three terminals. The fourth terminal can take the form of a second cathode-type structure, a second base region or a Schottky gate electrode. The cathode region and fourth terminal are in proximity enough to each other such that one of the cathode region and the fourth terminal is usable as an input terminal and that the other of the cathode region and the fourth terminal is usable as a terminal to which an electrical signal for disturbing an electric field profile or a current density in the active region is applied.Type: GrantFiled: March 30, 2001Date of Patent: May 20, 2003Assignee: Sharp Kabushiki KaishaInventor: John Kevin Twynam
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Patent number: 6559470Abstract: An improved negative differential resistance field effect transistor (NDR-FET) is disclosed. The NDR FET includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. In this fashion, charge traps can be optimized for extremely rapid trapping and de-trapping of charge because they are extremely close to a channel of hot carriers. The NDR-FET is also useable as a replacement for conventional NDR diode and similar devices in memory cells, and enables an entire family of logic circuits that only require a single channel technology (i.e., instead of CMOS) and yet which provide low power.Type: GrantFiled: December 21, 2001Date of Patent: May 6, 2003Assignee: Progressed Technologies, Inc.Inventor: King Tsu-Jae
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Publication number: 20030062536Abstract: The invention relates to new mono-, oligo- and poly-difluorovinyl(hetero)arylenes comprising one or more identical or different recurring units of formula I 1Type: ApplicationFiled: July 24, 2002Publication date: April 3, 2003Applicant: Merck Patent GmbHInventors: Martin Heeney, Louise Farrand, Mark Giles, Marcus Thompson, Steven Tierney, Maxim Shkunov, David Sparrowe, Iain McCulloch
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Patent number: 6528827Abstract: An MSM semiconductor circuit formed on a semi-insulating substrate that includes a set of contacts, first and second absorption layers, and a wide band gap buffer layer. The first absorption layer is formed on the semi-insulating substrate. The second absorption layer operably coupled to the set of contacts. The wide band gap buffer layer disposed between the first absorption layer and the second absorption layer.Type: GrantFiled: March 7, 2001Date of Patent: March 4, 2003Assignee: OptoLynx, Inc.Inventor: Jason P. Henning
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Patent number: 6417531Abstract: A charge transfer device has a charge transfer region under charge transfer electrodes for stepwise conveying charge packets through potential wells to a floating diffusion region, and the charge transfer region has a boundary sub-region contracting toward the floating diffusion region, wherein the final potential well is created at a certain portion in said boundary sub-region close to the floating diffusion region so that each charge packet travels over a short distance, thereby enhancing a charge transfer efficiency.Type: GrantFiled: October 27, 1999Date of Patent: July 9, 2002Assignee: NEC CorporationInventor: Yasutaka Nakashiba
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Publication number: 20020017661Abstract: To transfer signal charges at high speed with small noise, there is provided a charge transfer apparatus including a semiconductor substrate of one conductivity type, a charge transfer region of a conductivity type opposite to that of the semiconductor substrate that is formed in the semiconductor substrate and joined to the semiconductor substrate to form a diode, a signal charge input portion which inputs a signal charge to the charge transfer region, a signal charge output portion which accumulates the signal charge transferred from the charge transfer region, and a plurality of independent potential supply terminals which supply a potential gradient to the semiconductor substrate, wherein the signal charge in the charge transfer region is transferred by the potential gradient formed by the plurality of potential supply terminals.Type: ApplicationFiled: June 7, 2001Publication date: February 14, 2002Inventor: Mahito Shinohara
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Publication number: 20010028066Abstract: The invention provides a signal processing apparatus comprising clamp capacitance means for receiving, at one electrode thereof, first and second signals outputted from a signal source, a signal transfer transistor of which one main electrode is connected to an other electrode of the clamp capacitance means, signal accumulating capacitance means connected to an other main electrode of the signal transfer transistor, and reset means for fixing the potential of the signal accumulating capacitance means, wherein the potential of the signal accumulating capacitance means is fixed by the reset means while the first signal is outputted from the signal source and the signal accumulating capacitance means is maintained in a floating state while the second signal is outputted from the signal source, and the signal transfer transistor is controlled in such a manner that the potential of the main electrode of the signal transfer transistor and that of the other main electrode thereof show different saturation operationsType: ApplicationFiled: February 27, 2001Publication date: October 11, 2001Inventors: Mahito Shinohara, Tomoyuki Noda