Abstract: A method including depositing an alloying layer along a sidewall of an opening and in direct contact with a seed layer, the alloying layer includes a crystalline structure that cannot serve as a seed for plating a conductive material, exposing the opening to an electroplating solution including the conductive material, the conductive material is not present in the alloying layer, applying an electrical potential to a cathode causing the conductive material to deposit from the electroplating solution onto the cathode exposed at the bottom of the opening and causing the opening to fill with the conductive material, the cathode includes an exposed portion of the seed layer and excludes the alloying layer, and forming a first intermetallic compound along an intersection between the alloying layer and the conductive material, the first intermetallic compound is formed as a precipitate within a solid solution of the alloying layer and the conductive material.

Abstract: One illustrative method disclosed herein includes forming a patterned hard mask layer comprised of a plurality of discrete openings above a structure, wherein the patterned hard mask layer is comprised of a plurality of intersecting line-type features, forming a patterned etch mask above the patterned hard mask layer that exposes at least one, but not all, of the plurality of discrete openings, and performing at least one etching process through the patterned etch mask and the at least one exposed opening in the patterned hard mask layer to define an opening in the structure.

Abstract: The memory cell includes a memory area which is formed in a phase-change material pattern based on chalcogenide. An electric p/n-type junction is series-connected between electrodes. The p/n junction is formed in a crystalline area by the interface between first and second doped areas of the phase-change material pattern. The memory area is formed in one of the two doped areas, at a distance from the junction.

Abstract: A structure for a variable-resistance element using an electrochemical reaction. The structure limits a position at which metal cross-linking breaks to a position most preferred for cross-linking break: namely, a part of an ion conduction layer closest to a first electrode. Also provided is a method for manufacturing the variable-resistance element, which has a first electrode serving as a source for a metal ion(s), a second electrode which is less ionizable (i.e. has a higher redox potential) than the first electrode, and an ion conduction layer which is interposed between the first and second electrodes and can conduct the metal ion(s). There is a first region in the ion conduction layer, adjacent to the first electrode, having a diffusion coefficient that increases continuously towards the first electrode right upto contacting the first electrode.

Abstract: A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line with a spacer of electrically insulating material surrounding the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, etching a gate contact region for the word line between the pair of pillars, forming a spacer of electrically insulating material in the gate contact region, and depositing a gate contact between the pair of pillars to be in electrical contact with the gate material such that the spacer surrounds the gate contact.

Abstract: A nonvolatile memory cell includes first and second electrodes. Programmable material and a select device are received in series between and with the first and second electrodes. Current conductive material is in series between and with the programmable material and the select device. An array of vertically stacked tiers of such nonvolatile memory cells is disclosed. Methods of forming arrays of nonvolatile memory cells are disclosed.

Abstract: A non-volatile memory device includes first wiring structures elongated in a first direction and separated by a first gap region in a second direction, the first gap region comprising first dielectric material formed in a first process, second wiring structures elongated in a second direction and separated by a second gap region in a first direction, the second gap region comprising second dielectric material formed in a second process, and a resistive switching devices comprising active conductive material, resistive switching material, and a junction material, wherein resistive switching devices are formed at intersections of the first wiring structures and the second wiring structures, wherein the junction material comprising p+ polysilicon material overlying the first wiring material, wherein some resistive switching devices are separated by the first gap region and some resistive switching devices separated by the second gap region.

Abstract: Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells.

Abstract: A method of storing a bit at a memory device is disclosed. A memory cell the memory device is formed of a germanium-deficient chalcogenide glass configured to alternate between an amorphous phase and a crystalline phase upon application of a selected voltage, wherein a drift coefficient of the germanium-deficient chalcogenide glass is less than a drift coefficient of an undoped chalcogenide glass. A voltage is applied to the formed memory cell to select one of the amorphous phase and the crystalline phase to store the bit.

Abstract: A non-volatile memory device includes first wiring structures elongated in a first direction and separated by a first gap region in a second direction, the first gap region comprising first dielectric material formed in a first process, second wiring structures elongated in a second direction and separated by a second gap region in a first direction, the second gap region comprising second dielectric material formed in a second process, and a resistive switching devices comprising active conductive material, resistive switching material, and a junction material, wherein resistive switching devices are formed at intersections of the first wiring structures and the second wiring structures, wherein the junction material comprising p+ polysilicon material overlying the first wiring material, wherein some resistive switching devices are separated by the first gap region and some resistive switching devices separated by the second gap region.

Abstract: A manufacturing method includes forming, on a substrate, lower layer copper lines each being shaped into a strip, forming electrode seed layers each being shaped into a strip, on the respective lower layer copper lines using electroless plating, forming an interlayer insulating layer above the electrode seed layers, forming, in the interlayer insulating layer, memory cell holes, penetrating through the interlayer insulating layer and extending to the electrode seed layers, forming noble metal electrode layers on the electrode seed layers exposed in the respective memory cell holes using the electroless plating, forming, in the respective memory cell holes, variable resistance layers connected to the noble electrode layers, and forming, above the interlayer insulating layer and the variable resistance layers, upper layer copper lines each being shaped into a strip, connected to a corresponding one of the variable resistance layers, and crossing the lower layer copper lines.

Abstract: A method of manufacturing a semiconductor device comprises: forming a processing target; forming a first supporter on the processing target; forming a first mask so as to contact one side surface of the first mask with a side surface of the first supporter; patterning the processing target using, as masks, the first mask and the first supporter; forming a second supporter so as to be contacted with a side surface of the processing target exposed in first processing step and the other side surface of the first mask; removing the first supporter; and patterning the processing target using, as masks, the first mask and the second supporter.

Abstract: A phase change memory cell has first and second electrodes having phase change material there-between. The phase change memory cell is devoid of heater material as part of either of the first and second electrodes and being devoid of heater material between either of the first and second electrodes and the phase change material. A method of forming a memory cell having first and second electrodes having phase change material there-between includes lining elevationally inner sidewalls of an opening with conductive material to comprise the first electrode of the memory cell. Elevationally outer sidewalls of the opening are lined with dielectric material. Phase change material is formed in the opening laterally inward of and electrically coupled to the conductive material in the opening. Conductive second electrode material is formed that is electrically coupled to the phase change material. Other implementations are disclosed.

Abstract: In a first aspect, a memory cell is provided that includes (1) a first conductor; (2) a reversible resistance-switching element formed above the first conductor including (a) a carbon-based resistivity switching material; and (b) a carbon-based interface layer coupled to the carbon-based resistivity switching material; (3) a steering element formed above the first conductor; and (4) a second conductor formed above the reversible resistance-switching element and the steering element. Numerous other aspects are provided.

Abstract: A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line with a spacer of electrically insulating material surrounding the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, etching a gate contact region for the word line between the pair of pillars, forming a spacer of electrically insulating material in the gate contact region, and depositing a gate contact between the pair of pillars to be in electrical contact with the gate material such that the spacer surrounds the gate contact.

Abstract: A semiconductor memory device and a method for fabricating the same capable of easily controlling a contact area between a conductive line and a memory layer even at the high degree of integration. The semiconductor memory device includes a plurality of first conductive lines, a memory layer contacting with a first sidewall of each of the first conductive lines, and a plurality of second conductive lines crossing the first conductive lines and contacting with the memory layer.

Abstract: The disclosure provides a non-volatile memory structure and a method for fabricating the same. The non-volatile memory structure includes a first contact connected to a first transistor. A second contact is connected to a second transistor. A resistance-changing memory material pattern covers and contacts the second contact but not the first contact. A top electrode contacts both the resistance-changing memory material pattern and the first contact. An area of the resistance-changing memory material pattern is substantially larger than an area of its interface with the second contact.

Abstract: A method for fabricating a variable resistance memory device in accordance with an embodiment of the present invention includes: sequentially forming a first conductive layer and a variable resistance layer on a substrate; forming stacked structures in which first conductive lines and variable resistance lines are sequentially stacked by selectively etching the variable resistance layer and the first conductive layer; forming an insulating layer to fill a space between the stacked structures; forming a second conductive layer on the insulating layer and the stacked structures; and forming a second conductive line and a variable resistance pattern by etching the second conductive layer and the variable resistance line using mask patterns in a line type extending in a direction intersecting the stacked structures.

Abstract: A memory device includes a substrate and a memory array on the substrate. The memory array includes memory cells including stressed phase change materials in a layer of encapsulation materials. The memory cells may include memory cell structures such as mushroom-type memory cell structures, bridge-type memory cell structures, active-in-via type memory cell structures, and pore-type memory cell structures. The stressed phase change materials may comprise GST (GexSbxTex) materials in general and Ge2Sb2Te5 in particular. To manufacture the memory device, a substrate is first fabricated. Memory cells including phase change materials in a layer of encapsulation materials are formed on a front side of the substrate. A tensile or compressive stress is induced into the phase change materials on the front side of the substrate.

Abstract: A phase change memory device including a multi-level cell and a method of manufacturing the same are provided. The device includes a first phase-change material layer to which a current is provided from a heating electrode, and a second phase-change material layer formed with continuity to the first phase-change material layer and having a different width from the first phase-change material layer, and to which a current is provided from a heating electrode.

Abstract: A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

Abstract: A resistive switching nonvolatile memory device having an interface layer disposed between a doped silicon electrode and a variable resistance layer fabricated in the nonvolatile memory device and methods of fabricating the same. In one embodiment, the interface layer is a high-k layer having a lower electrical EOT than native silicon oxide to act as a diffusion barrier between the variable resistance layer and the silicon electrode. Alternatively, the high-k interface layer may be formed by performing a nitrogen treatment on a fabricated silicon oxide layer. In another embodiment, the interface layer may be fabricated by performing a nitrogen or ozone treatment on the native oxide layer. In another embodiment, the interface layer is a fabricated silicon oxide layer resulting in an improved diffusion barrier between the variable resistance layer and the silicon electrode. In all embodiments, the interface layer also passivates the surface of the silicon electrode.

Abstract: A method of forming a phase change material layer pattern includes forming a phase change material layer partially filling an opening through an insulating interlayer. A plasma treatment process is performed on the phase change material layer to remove an oxide layer on a surface of the phase change material layer. A heat treatment process is performed on the phase change material layer to remove a void or a seam in the phase change material layer, sufficiently filling the opening.

Abstract: According to one embodiment, a resistance change memory includes resistance change elements, vias and sidewall insulating layers, the elements and the vias provided alternately in a first direction and a second direction orthogonal to the first direction, and the sidewall insulating layers provided on sidewalls of the elements. The elements are provided in a lattice pattern having a constant pitch. A thickness of each of the sidewall insulating layers in a direction orthogonal to the sidewalls is a value for contacting the sidewall insulating layers each other or more to form holes between the sidewall insulating layers. The vias are provided in the holes respectively.

Abstract: A method of manufacturing a semiconductor device comprises: forming a processing target; forming a first supporter on the processing target; forming a first mask so as to contact one side surface of the first mask with a side surface of the first supporter; patterning the processing target using, as masks, the first mask and the first supporter; forming a second supporter so as to be contacted with a side surface of the processing target exposed in first processing step and the other side surface of the first mask; removing the first supporter; and patterning the processing target using, as masks, the first mask and the second supporter.

Abstract: In a method of fabricating a semiconductor device, a target layer and a first material layer are sequentially formed on a substrate. A plurality of second material layer patterns are formed on the first material layer, the second material layer patterns extending in a first horizontal direction. A plurality of hardmask patterns extending in a second horizontal direction are formed on the plurality of second material layer patterns and the first material layer, wherein the second horizontal direction is different from the first horizontal direction. A first material layer pattern is formed by etching the first material layer using the plurality of hardmask patterns and the plurality of second material layer patterns as etch masks. A target layer pattern with a plurality of holes is formed by etching the target layer using the first material layer pattern as an etch mask.

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract: The present disclosure relates to the microelectronics field, and particularly, to a metal oxide resistive switching memory and a method for manufacturing the same. The method may comprise: forming a W-plug lower electrode above a MOS device; sequentially forming a cap layer, a first dielectric layer, and an etching block layer on the W-plug lower electrode; etching the etching block layer, the first dielectric layer, and the cap layer to form a groove for a first level of metal wiring; sequentially forming a metal oxide layer, an upper electrode layer, and a composite layer of a diffusion block layer/a seed copper layer/a plated copper layer in the groove for the first level of metal wiring; patterning the upper electrode layer and the composite layer by CMP, to form a memory cell and the first level of metal wiring in the groove in the first dielectric layer; and performing subsequent processes to complete the metal oxide resistive switching memory.

Abstract: A phase change material may be processed to reduce its microcrystalline grain size and may also be processed to increase the crystallization or set programming speed of the material. For example, material doped with nitrogen to reduce grain size may be doped with titanium to reduce crystallization time.

Abstract: Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions.

Abstract: An improved method of fabricating a resistive memory device is disclosed. A resistive memory includes a bottom electrode, a top electrode and a resistive material layer interposed therebetween. Interfaces are formed between the resistive material layer and the respective top and bottom electrodes. Ions are implanted in the device to change the characteristics of one or both of these interfaces, thereby improving the performance of the memory device. These ions may be implanted after the three layers are fabricated, during the fabrication of these layers, or at both times.

Abstract: A structure for a variable-resistance element using an electrochemical reaction. The structure limits a position at which metal cross-linking breaks to a position most preferred for cross-linking break: namely, a part of an ion conduction layer closest to a first electrode. Also provided is a method for manufacturing the variable-resistance element, which has a first electrode serving as a source for a metal ion(s), a second electrode which is less ionizable (i.e. has a higher redox potential) than the first electrode, and an ion conduction layer which is interposed between the first and second electrodes and can conduct the metal ion(s). There is a first region in the ion conduction layer, adjacent to the first electrode, having a diffusion coefficient that increases continuously towards the first electrode right upto contacting the first electrode.

Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material.

Abstract: A non-volatile memory is disclosed. A contiguous layer of phase change material is provided. Proximate the contiguous layer of phase change material is provided a first pair of contacts for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a first region. Also adjacent the contiguous layer is provided a second pair of contacts disposed for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a second region thereof, the second region different from the first region.

Abstract: A nonvolatile memory cell includes first and second electrodes. Programmable material and a select device are received in series between and with the first and second electrodes. Current conductive material is in series between and with the programmable material and the select device. An array of vertically stacked tiers of such nonvolatile memory cells is disclosed. Methods of forming arrays of nonvolatile memory cells are disclosed.

Abstract: A graphene-based device can be characterized as including a first electrode comprising graphene, a second electrode comprising graphene, and a potential barrier. The first electrode is physically separated from the second electrode by the potential barrier. The first electrode, second electrode and potential barrier are configured such that the graphene-based device can exhibit non-linear I-V characteristics under application of a voltage bias between the first electrode and the second electrode.

Abstract: Provided are semiconductor memory devices and the methods of fabricating the same. The method may include forming a plurality of diode patterns in each of a plurality of first trenches, each of the plurality of first trenches including at least two active regions, the plurality of diode patterns occupying a plurality of spaces, treating the plurality of diode patterns to form a plurality of semiconductor patterns in each of the plurality of spaces, removing portions of the plurality of semiconductor patterns to form a recess in each of the plurality of spaces, treating the of the plurality of semiconductor patterns to form a plurality of diodes in each of the plurality of spaces, forming a bottom electrode on each of the plurality of diodes, forming a plurality of memory elements on each of the bottom electrodes, and forming a plurality of upper interconnection lines on the plurality of memory elements.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: A step of forming, on a substrate (11), lower layer copper lines (18) each being shaped into a strip, a step of forming electrode seed layers (21) each being shaped into a strip, on the surfaces of the respective lower layer copper lines (18) using electroless plating, a step of forming interlayer insulating layer (19) above the electrode seed layers (21) and the substrate (11), a step of forming, in the interlayer insulating layer (19), memory cell holes (20), penetrating through the interlayer insulating layer (19) and extending to the electrode seed layers (21), a step of forming noble metal electrode layers (29) on the surfaces of the electrode seed layers (21) exposed in the respective memory cell holes (20) using the electroless plating, a step of forming, in the respective memory cell holes (20), variable resistance layers (23) connected to the noble electrode layers (29), and a step of forming, above the interlayer insulating layer (19) and the variable resistance layers (23), upper layer copper lines

Abstract: The objective of the present invention is to provide a semiconductor device provided with a resistance-variable element having sufficient switching property and exhibiting high reliability and high densification as well as good insulating property. The present invention provides a semiconductor device comprising a resistance-variable element provided within multiple wiring layers on a semiconductor substrate, wherein the resistance-variable element comprises a laminated structure in which a first electrode, a first ion-conductive layer of valve-metal oxide film, a second ion-conductive layer containing oxygen and a second electrode are laminated in this order, and the wiring of the multiple wiring layers also serves as the first electrode.

Abstract: Phase change memory cell structures and methods are described herein. A number of methods of forming a phase change memory cell structure include forming a dielectric stack structure on a first electrode, wherein forming the dielectric stack structure includes creating a second region between a first region and a third region of the dielectric stack structure, the second region having a thermal conductivity different than a thermal conductivity of the first region and different than a thermal conductivity of the third region of the dielectric stack. One or more embodiments include forming a via through the first, second, and third regions of the dielectric stack structure, depositing a phase change material in the via, and forming a second electrode on the phase change material.

Abstract: According to one embodiment, a semiconductor device includes a plurality of silicon films. The plurality of silicon films are disposed on one plane and are made of polysilicon containing an impurity. A crystal orientation of each of the silicon films is a (311) orientation.

Abstract: An electronic device comprises a variable resistance memory element on a substrate. The variable resistance memory element comprises (i) an amorphous carbon layer comprising a hydrogen content of at least about 30 atomic percent, and a maximum leakage current of less than about 1×10?9 amps, and (ii) a pair of electrodes about the amorphous carbon layer. Methods of fabricating this and other devices are also described.

Abstract: A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction.

Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Abstract: A phase change memory device is provided, including a substrate, a first dielectric layer disposed over the substrate, a first electrode disposed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, covering the first electrode, a heating electrode disposed in the second dielectric layer, contacting the first electrode, a phase change material layer disposed over the second dielectric layer, contacting the heating electrode, and a second electrode disposed over the phase change material layer. In one embodiment, the heating electrode includes a first portion contacting the first electrode and a second portion contacting the phase change material layer, and the second portion of the heating electrode includes metal silicides and the first portion of the heating electrode includes no metal silicides.

Abstract: A method of manufacturing a phase change memory (PCM) includes forming a pinch plate layer transversely to a PCM layer that is insulated from the pinch plate layer by a dielectric layer. Biasing the pinch plate layer causes a depletion region to form in the PCM layer. During a read of the PCM in a reset or partial reset state the depletion region increases the resistance of the PCM layer significantly.

Abstract: A technique used for a semiconductor device formed by stacking multiple structural bodies each having a semiconductor device, for preventing generation of thermal load on a structural body at a lower layer which is caused by a laser used in a step of forming a structural body at an upper layer. In a phase-change memory including multiple stacked memory matrices, a metal film is disposed between a memory matrix at a lower layer and a memory matrix at an upper layer formed over the memory matrix at the lower layer, in which the laser used for forming the memory matrix is reflected at the metal film and prevented from transmitting the metal film, thereby preventing the phase-change material layer, etc. in the memory matrix at the lower layer from being directly heated excessively by the laser.

Abstract: Provided are variable resistance memory devices and methods of forming the variable resistance memory devices. The methods can include forming an etch stop layer on an electrode, forming a molding layer on the etch stop layer, forming a recess region including a lower part having a first width and an upper part having a second width by recessing the etch stop layer and the molding layer, and forming a layer of variable resistance material in the recess region.