Abstract: A circuit includes a solid-state relay, a rectifier, and a current transformer-based power supply. The rectifier is adapted to be coupled to the solid-state relay. The rectifier is configured to provide a voltage to an output terminal responsive to the solid-state relay being in an off state. The current transformer-based power supply is coupled to the rectifier and is adapted to be coupled to a transformer. The current transformer-based power supply is configured to provide a voltage to the output terminal responsive to the solid-state relay being in an on state.

Abstract: In an induction motor group control system, magnetic energy recovery switches (3) are connected in series to an induction motor (2) directly driven by a commercial power supply, and a plurality of induction motor control devices (10) enabling voltage control and reactive power control of the induction motor 2 are employed to control generation of reactive power so as to maximize a power factor of the entire plurality of AC loads including the induction motor or compensate variations in voltage of an AC power supply (1).

Abstract: A logic circuit associated with a scan path circuit includes at least one clock controller and at least one scan flipflop. The clock controller includes a first control gate receiving a clock signal and a scan mode signal and configured to maintain its output at a fixed value when the scan mode signal is active, a second control gate receiving an output of the first control gate and a first test clock signal for generating a first enable signal, and a third control gate receiving an output of the second control gate and a second test clock signal for generating a second enable signal. The scan flipflop includes a selector having a pair of inputs receiving a data input signal and a scan input signal, respectively, and also having a selection input receiving the scan mode signal so that when the scan mode signal is active, the scan input signal is selected, and when the scan mode signal is inactive, the data input signal is selected.

Abstract: A semiconductor integrated circuit device wherein terminals other than clock signal terminals in circuit blocks are connected via a first wiring layer to a clock signal source and only the clock signal terminals in the blocks are connected via a second wiring layer to the source. The second wiring layer is formed above the first wiring layer and is connected to the clock signal terminals. Since the second wiring layer is dedicated to the clock signal, clock signal wiring can be laid out as desired when a layout is designed by a hierarchical design technique. There is no chance that propagation characteristics of the clock signals to the blocks deviates, and a cell area can be reduced. Preferably, a third wiring layer connected to the second wiring layer is furthermore provided for dedication to the clock signal.