Abstract: One or more devices in a data analysis computing system may be configured to receive and analyze movement data and driving data, and determine driving trips and associated drivers based on the received data. Movement data may be collected by one or more mobile devices, such as smartphones, tablet computers, and on-board vehicle systems. Drivers associated with driving trips may be identified based on the movement data collected by the mobile devices, such as speed data, acceleration data, or distance data.

Abstract: A method of tracking objects using a radar, includes sending a beamcode to at least one radar antenna to set a predetermined direction, using samples from a random distribution of at least one of a phase or an amplitude to generate a tracking signal pulse train, transmitting the pulse train from the at least one antenna within a pulse time window, receiving return signals from objects at the at least one antenna, and using the return signals to gather data to track the objects. A radar system has at least one radar antenna to transmit a tracking signal, a memory to store a set of random distributions, a controller connected to at least one radar antenna and the memory, the controller to execute instructions to determine which random distribution to use, generate a pulse train using the random distribution, transmit the pulse train to the at least one radar antenna as the tracking signal, and gather measurement data about objects returning signals from the tracking signal.

Abstract: The various technologies presented herein relate to correcting a time-dependent phase error generated as part of the formation of a radar waveform. A waveform can be pre-distorted to facilitate correction of an error induced into the waveform by a downstream operation/component in a radar system. For example, amplifier power droop effect can engender a time-dependent phase error in a waveform as part of a radar signal generating operation. The error can be quantified and an according complimentary distortion can be applied to the waveform to facilitate negation of the error during the subsequent processing of the waveform. A time domain correction can be applied by a phase error correction look up table incorporated into a waveform phase generator.

Abstract: An apparatus for determining a number of successive equal bits preceding an edge within a bit stream including a repetitive bit sequence includes an edge number determiner, an edge selector, a time stamper and an equal bits determiner. The edge number determiner determines a preset number of edges. The preset number of edges is coprime to a number of edges of the repetitive bit sequence or coprime to a maximal number of edges of the repetitive bit sequence. The edge selector selects edges of the bit stream spaced apart from each other by the preset number of edges. Further, the time stamper determines a time stamp for each selected edge of the bit stream and the equal bits determiner determines the number of successive equal bits preceding the edge based on determined time stamps of selected edges.

Abstract: Systems and methods for processing image signals are described. One method comprises obtaining a generator signal based on an image signal and determining relative latencies associated with two or more pulses in a pulsed signal using a function of the generator signal that can comprise a logarithmic function. The function of the generator signal can be the absolute value of its argument. Information can be encoded in the pattern of relative latencies. Latencies can be determined using a scaling parameter that is calculated from a history of the image signal. The pulsed signal is typically received from a plurality of channels and the scaling parameter corresponds to at least one of the channels. The scaling parameter may be adaptively calculated such that the latency of the next pulse falls within one or more of a desired interval and an optimal interval.

Abstract: The invention provides an apparatus and a method for performing a calculation operation with at least one input signal consisting of signal sections, wherein each signal section of said input signal has a constant amplitude. The apparatus comprises a signal transformation unit for transforming at least one input signal into a first intermediary signal having a virtual amplitude with respect to at least one carrier signal. The calculation unit is provided for performing the calculation operation on said first intermediary signal to generate a second intermediary signal. A signal re-transformation unit re-transforms the second intermediary signal into an output signal consisting of signal sections, wherein each signal section of said output signal has a constant amplitude.

Abstract: Circuits, methods, and apparatus for adjusting an NCO output in order to provide a signal that is phase-locked to a reference signal. This is particularly beneficial where the frequencies of the NCO output and reference signal are unrelated. One embodiment provides a circuit that corrects the phase of the NCO output in two steps in order to reduce the chance of metastability. During the first, the output of the NCO is phase shifted to the closest correct portion of a cycle of a clock signal. A second correction is then performed by steering a number of currents under the control of at least some of a number of remainder bits from the NCO. The current steering provides a die area efficient, low-noise phase correction. The decoded remainder bits are latched using a feed forward circuit that prevents the device from entering a locked state.

Abstract: A finite impulse response filter is implemented as a sum of individual component, running-sum filters. The sum of all of the component filters required for a desired filter response is calculated in an accumulator and only the component filters' update terms, which are the difference between a new and an old discarded sample, is calculated for each component filter. A desired impulse response is decomposed into a sum of rectangular impulse responses of equal height, each of which implemented as a running sum requiring a subtraction and an addition. Using circuits running at a multiple of the sampling clock, multiple running sums may be implemented on the same hardware. A whole filter of arbitrary impulse response shapes and lengths may be implemented using memory and two arithmetic units. Two or more such filters may be cascaded to obtain a better approximation of the desired frequency characteristic. The invention saves significant chip resources and manufacturing costs.

Abstract: A method and apparatus for reducing unwanted harmonics in direct digital synthesizer (DDS) output. The method comprises the steps of providing a set of k phase-shifted clock signals, examining, in succession, each DDS accumulator state, and determining whether the DDS accumulator state has a defined transition-state. For each DDS accumulator state having a defined transition-state, an interpolation is performed based upon the value of the preceding DDS accumulator state, an element of the set of phase-shifted clock signals is selected based upon the interpolation, and the most significant bit (MSB) is repositioned using the selected element of the phase-shifted clock signals. The apparatus comprises means for providing a set of k phase-shifted clock signals, means for examining, in succession, each DDS accumulator state, and means for determining whether the DDS accumulator state has a defined transition-state.