Abstract: There is disclosed example techniques to include obtaining a filtering rule via a control plane message that includes information to identify a source of a general packet radio service (GPRS) tunneling protocol (GTP) user-plane (GTP-U) packet. The example techniques also include configuring, based on the information to identify the source, a virtual switch to identify the source of the GTP-U packet to use in the filtering rule to cause a received GTP-U packet to be sent to a local edge server or a mobile core network for processing based on at least a portion of a first extension header included in the GTP-U packet.

Abstract: Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.

Abstract: An active filter and an analog-to-digital converter (ADC) configured to suppress out-of-band peaking. An active filter may include an active device configured to provide a power gain to an input signal, a feedback network configured to connect an output of the active device to an input of the active device, and an input impedance network configured to couple the input signal to the input of the active device. A combination of the feedback network and the input impedance network is configured to provide frequency response properties of the active filter such that a frequency domain signal transfer function of the active filter has a constant in numerator.

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

Abstract: Various embodiments herein provide physical uplink control channel (PUCCH) designs for discrete Fourier transform-spread-orthogonal frequency-division multiplexing (DFT-s-OFDM) waveforms for systems operating above the 52.6 GHz carrier frequency. Some embodiments of the present disclosure may be directed to phase tracking reference signal (PT-RS) design for PUCCH with carrier frequencies above 52.6 GHz. Other embodiments may be disclosed and/or claimed.

Abstract: Various systems and methods for providing opportunistic placement of compute in an edge network are described herein. A node in an edge network may be configured to access a service level agreement related to a workload, the workload to be orchestrated for a user equipment by the node; modify a machine learning model based on the service level agreement; implement the machine learning model to identify resource requirements to execute the workload in a manner to satisfy the service level agreement; initiate resource assignments from a resource provider, the resource assignments to satisfy the resource requirements; construct a resource hierarchy from the resource assignments; initiate execution of the workload using resources from the resource hierarchy; and monitor and adapt execution of the workload based on the resource hierarchy in response to the execution of the workload.

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

Abstract: An apparatus and system to enable URLLC PUSCH repetitions in the unlicensed spectrum are described. The number of consecutive PUSCH repetitions indicated in the RRC parameter is reinterpreted as the number of transmission occasions over which the UE is able to attempt CCA. An orphan symbol is used to provide a DMRS transmission or cyclic prefix of the PUSCH transmission causing the orphan symbol. Whether a CG-UCI is piggybacked in a PUSCH transmission, and whether DCI-DFI is used, is dependent on whether cg-RetransmissionTimer is configured.

Abstract: Apparatuses, methods and storage medium associated with compensating for a sensor deficiency in a heterogeneous sensor array are disclosed herein. In embodiments, an apparatus may include a compute device to aggregate perception data from individual perception pipelines, each of which is associated with respective one of different types of sensors of a heterogeneous sensor set, to identify a characteristic associated with a space to be monitored by the heterogeneous sensor set; detect a sensor deficiency associated with a first sensor of the sensors; and in response to a detection of the sensor deficiency, derive next perception data for more than one of the individual perception pipelines from sensor data originating from at least one second sensor of the sensors. Other embodiments may be disclosed or claimed.

Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

Abstract: Technologies for establishing device locality are disclosed. A processor in a computing device generates an identifier distinct to the computing device. The processor transmits the identifier to a management controller via a hardware bus in the computing device. The processor generates a key and encrypts the key with the identifier to generate a wrapped key. The processor transmits the wrapped key to the management controller. In turn, the management controller unwraps the key using the identifier. Other embodiments are described and claimed.

Abstract: A method comprises generating, for a cacheline, a first tag and a second tag, the first tag and the second tag generated as a function of user data stored and metadata in the cacheline stored in a first memory device, and a multiplication parameter derived from a secret key, storing the user data, the metadata, the first tag and the second tag in the first cacheline of the first memory device; generating, for the cacheline, a third tag and a fourth tag, the third tag and the fourth tag generated as a function of the user data stored and metadata in the cacheline stored in a second memory device, and the multiplication parameter; storing the user data, the metadata, the third tag and the fourth tag in the corresponding cache line of the second memory device; receiving, from a requesting device, a read operation directed to the cacheline; and using the first tag, the second tag, the third tag, and the fourth tag to determine whether a read error occurred during the read operation.

Abstract: Technologies for providing accelerated functions as a service in a disaggregated architecture include a compute device that is to receive a request for an accelerated task. The task is associated with a kernel usable by an accelerator sled communicatively coupled to the compute device to execute the task. The compute device is further to determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request. Additionally, the compute device is to assign the task to the determined accelerator sled for execution. Other embodiments are also described and claimed.

Abstract: Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

Abstract: Various embodiments herein provide techniques for reference signal (RS) configuration for high frequency bands (e.g., frequency above 52.6 GHz). For example, embodiments may include techniques for configuration of a demodulation reference signal (DM-RS), a channel state information reference signal (CSI-RS), and/or a sounding reference signal (SRS). The RS configuration may provide a low peak-to-average power ratio (PAPR) compared to prior techniques. Other embodiments may be described and claimed.

Abstract: Embodiments of the present disclosure may relate to the existence of a unique value associated with each PCIe function or device that is readable from two or more PCIe functions, or from a CPU running system software. Embodiments enable system software to identify which PCIe functions have private or hidden connections. In addition, embodiments may allow system software to differentiate among multiple identical instances of PCIe add-in components that have associations. Other embodiments may be described and/or claimed.

Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.

Abstract: Apparatus and method for compression of acceleration structure build data in a ray tracing implementation. For example, one embodiment of an apparatus comprises: traversal hardware logic to traverse rays through a graphics scene comprising a plurality of primitives; and an acceleration data structure processing unit comprising: a bounding box compressor to compress a set of bounding boxes to generate a plurality of bounding box compression blocks, and an index compressor to compress a set of indices to generate a plurality of index compression blocks, and an acceleration data structure builder for constructing acceleration structures based on bounding box compression blocks and index compression blocks.