Abstract: A process for depositing a metal includes disposing an activating catalyst on a substrate; contacting the activating catalyst with a metal cation from a vapor deposition composition; contacting the substrate with a reducing anion from the vapor deposition composition; performing an oxidation-reduction reaction between the metal cation and the reducing anion in a presence of the activating catalyst; and forming a metal from the metal cation to deposit the metal on the substrate. A system for depositing a metal includes an activating catalyst to deposit on a substrate; and a primary reagent to form: a metal cation to deposit on the substrate as a metal; and a reducing anion to provide electrons to the activating catalyst, the metal cation, the substrate, or a combination thereof, wherein the primary reagent forms the metal cation and the reducing anion in response to being subjected to a dissociating condition.

Abstract: A pressure sensor using the MEMS device comprises an airtight ring surrounding a chamber defined by the first substrate and the second substrate. The airtight ring extends from the upper surface of the second substrate to the interface between the first substrate and the second substrate and further breaks out the interface. The pressure sensor utilizes the airtight ring to retain the airtightness of the chamber.

Abstract: An alloy comprising about 0.5 weight percent to about 2 weight percent carbon, about 15 weight percent to about 30 weight percent chromium, about 4 weight percent to about 12 weight percent nickel, up to about 3 weight percent manganese, up to about 2.5 weight percent silicon, up to about 1 weight percent zirconium, up to about 3 weight percent molybdenum, up to about 3 weight percent tungsten, up to about 0.5 weight percent boron, up to about 0.5 weight percent impurities, and iron.

Abstract: A nitride semiconductor element includes a sapphire substrate including: a main surface extending in a c-plane of the sapphire substrate, and a plurality of projections disposed at the main surface, the plurality of projections including at least one projection having an elongated shape in a plan view; and a nitride semiconductor layer disposed on the main surface of the sapphire substrate. The at least one projection has an outer edge extending in a longitudinal direction of the elongated shape, the outer edge extending in a direction oriented at an angle in a range of ?10° to +10° with respect to an a-plane of the sapphire substrate in the plan view.

Abstract: An insulated gate turn-off (IGTO) device has a PNPN layered structure so that vertical NPN and PNP transistors are formed. Trench gates are formed extending into the intermediate P-layer. The device is formed of an array of cells. A P-channel MOSFET, having a trenched gate, is formed in some of the cells. The control terminal of the IGTO device is connected to the insulated gates of all cells, including to the gate of the P-channel MOSFET, and to the intermediate P-layer. To turn the device on, a positive voltage is applied to the control terminal to turn on the NPN transistor by forward biasing its base-emitter. To turn off the IGTO device, a negative voltage is applied to the control terminal to turn on the P-channel MOSFET to short the NPN base to its emitter.

Abstract: An epitaxial wafer comprises an epitaxial layer disposed on a substrate. The epitaxial layer comprises first to third semiconductor layers. The third semiconductor layer has a thickness that is thicker than that of the first semiconductor layer. A second doping density of the second semiconductor layer is between a first doping density of the first semiconductor layer and a third doping density of the third semiconductor layer.

Abstract: An image sensor device includes a substrate, a color filter layer, at least a pixel, a main isolation structure and a sub-isolation structure. The color filter layer is disposed over the substrate. The color filter layer includes a first color filter having a single one of primary colors. The pixel is disposed in the substrate and aligned with the first color filter. The main isolation structure surrounds the pixel in the substrate. The sub-isolation structure is disposed to divide the pixel into a plurality of sub-first pixels. The sub-pixels correspond to the first color filter having the single one of primary colors, and each of the sub-first pixels includes a radiation sensor.

Abstract: A semiconductor device including pixels arranged in a matrix of n rows and m columns, in which the pixels in the m-th column are shielded from light, is provided.

Abstract: Embodiments provide a light emitting device module including a circuit board, a light emitting device bonded to a conductive layer on the circuit board via a conductive adhesive, a phosphor layer disposed on a side surface and an upper surface of the light emitting device, and a lens on the circuit board and the phosphor layer. A void is generated between the light emitting device and the circuit board.

Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of fins formed thereon, a stress layer formed on the top surface of each of the fins, and a plurality of strip-shaped gate structures formed above the stress layers. The method further includes forming a contact hole etch stop layer. The method further includes forming a first interlayer dielectric layer to fill the gaps between adjacent fins. The first interlayer dielectric layer includes filling voids formed therein. The method further includes back etching the first interlayer dielectric layer to cause the top surface of the first interlayer dielectric layer to be just above the filling voids. The method further includes forming a barrier liner layer over the first interlayer dielectric layer, and forming a second interlayer dielectric layer over the barrier liner layer and the contact hole etch stop layer.

Abstract: Provided is a semiconductor device which can suppress an increase in oxygen vacancies in an oxide semiconductor layer and a manufacturing method of the semiconductor device. The semiconductor device includes a first oxide semiconductor layer over the first insulating layer; a second oxide semiconductor layer over the first oxide semiconductor layer; a third oxide semiconductor layer over the second oxide semiconductor layer; a source electrode layer and a drain electrode layer each over the third oxide semiconductor layer; a fourth semiconductor layer over the source and drain electrode layers, and the third oxide semiconductor layer; a gate insulating layer over the fourth oxide semiconductor layer; a gate electrode layer over the gate electrode layer and overlapping with the source and drain electrode layers, and the fourth oxide semiconductor layer; and a second insulating layer over the first insulating layer, and the source, gate, and drain electrode layers.

Abstract: A low temperature poly-silicon thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The method comprises: S1: sequentially forming an active layer (3), a gate insulation layer (4), a gate electrode (5) and an interlayer insulation layer (6) on a base substrate (1); S2: forming a first metal thin film layer (8); S3: performing a hydrogenation treatment on the active layer (3) and the gate insulation layer (6); S4: forming a second metal thin film layer (7), the second metal thin film layer (7) being used for forming a source electrode and a drain electrode.

Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.

Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices may include a substrate with a cell region and a peripheral region, a gate stack including gates stacked on the cell region of the substrate. At least one edge portion of the gate stack may have a staircase structure. The semiconductor devices may also include a channel that extend through the gate stack and is enclosed by a memory layer and at least two dummy patterns on the substrate. The at least two dummy patterns may be spaced apart from the gate stack and may be spaced apart from each other.

Abstract: The present invention provides a thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device. The thin film transistor comprises a gate, a source, a drain, a gate insulation layer, an active layer, a passivation layer, a first electrode connection line and a second electrode connection line. The gate, the source and the drain are provided in the same layer and comprise the same material. The gate insulation layer is provided above the gate, the active layer is provided above the gate insulation layer, and a pattern of the gate insulation layer, a pattern of the gate and a pattern of the active layer coincide with each other.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor.

Abstract: Integrated circuit devices may include a stack that includes channel regions and gate electrodes stacked in an alternating sequence in a vertical direction. The channel regions may include impurities having a first conductivity type. The integrated circuit devices may also include source/drain regions on respective opposing sides of the stack, and the source/drain regions may be spaced apart from each other in a horizontal direction and may include impurities having a second conductivity type that is different from the first conductivity type. The integrated circuit devices may further include extension regions that may be between respective ones of channel regions and one of the source/drain regions and may include impurities having the second conductivity type. Each of the extension regions may have a thickness in the vertical direction that is less than those of the channel regions and the one of the source/drain regions.

Abstract: A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.

Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.

Abstract: A sensing device includes an array of sensing elements. Each sensing element includes a thermal infrared sensor, configured to output an electric signal in response to an intensity of infrared radiation that is incident on the sensor. An individual reflector is formed integrally with the sensor at a location separated from the sensor by one quarter wave at a selected wavelength of the infrared radiation.