Patents Examined by Robert M Kunemund
  • Patent number: 12000060
    Abstract: A semiconductor crystal growth method and device are provided. The method comprises: obtaining an initial position of a graphite crucible when used in a semiconductor crystal growth process for the first time; obtaining a current production batch of the graphite crucible which characterizes a number of times of growth processes performed by the graphite crucible so far; and loading polysilicon raw materials into a quartz crucible sleeved in the graphite crucible based on the current production batch, wherein a total weight of the materials is called a charging amount, and the charging amount is adjusted based on the current production batch to keep an initial position of a silicon melt liquid surface in the quartz crucible stable while keeping the initial position of the graphite crucible unchanged. The present invention ensures the stability of each parameter in the crystal pulling process, and enhances the crystal pulling speed and quality.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: June 4, 2024
    Assignee: ZING SEMICONDUCTOR CORPORATION
    Inventors: Weimin Shen, Gang Wang, Hanyi Huang, Yun Liu
  • Patent number: 11988868
    Abstract: A mask material is deposited on a substrate or growth template. The substrate or growth template is compatible with crystalline growth of a crystalline optical material. Patterned portions of the mask material are removed to expose one or more regions of the substrate or growth template. The one or more regions have target shapes of one or more optical components. The crystalline optical material is selectively grown in the one or more regions to form the one or more optical components.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: May 21, 2024
    Assignee: XEROX CORPORATION
    Inventor: Thomas Wunderer
  • Patent number: 11982014
    Abstract: The present disclosure provides an apparatus for crystal growth. The apparatus may include a furnace chamber a temperature field device placed at least partially into the furnace chamber. The furnace chamber may be a non-closed structure, and the temperature field device may be sealed.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: May 14, 2024
    Assignee: MEISHAN BOYA ADVANCED MATERIALS CO., LTD.
    Inventors: Yu Wang, Weiming Guan, Zhenxing Liang
  • Patent number: 11982019
    Abstract: A crystal growth doping apparatus and a crystal growth doping method are provided. The crystal growth doping apparatus includes a crystal growth furnace and a doping device that includes a feeding tube inserted to the furnace body along an oblique insertion direction, and a storage cover and a gate tube that are disposed in the feeding tube. The feeding tube extends from an outer surface thereof to form a placement opening, and the placement opening is recessed from an edge thereof to form an upper recessed portion and a lower recessed portion along the oblique insertion direction. The storage cover includes a storage tank and a handle. When the storage cover is disposed in the gate tube body, the gate tube body is configured to isolate an inner space of the feeding tube from the placement opening.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: May 14, 2024
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Yu-Chih Chu, Tang-Chi Lin, Han-Sheng Wu, Hsien-Ta Tseng
  • Patent number: 11982015
    Abstract: Variations in wafer thickness due to non-uniform CVD depositions at angular positions corresponding to crystallographic orientation of the wafer are reduced by providing a ring below the susceptor having inward projections at azimuthal positions which reduce radiant heat impinging upon the wafer at positions of increased deposition.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: May 14, 2024
    Assignee: SILTRONIC AG
    Inventors: Joerg Haberecht, Stephan Heinrich, Reinhard Schauer, Rene Stein
  • Patent number: 11976380
    Abstract: A process for producing a monocrystalline layer of GaAs material comprises the transfer of a monocrystalline seed layer of SrTiO3 material to a carrier substrate of silicon material followed by epitaxial growth of a monocrystalline layer of GaAs material.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: May 7, 2024
    Assignee: SOITEC
    Inventor: Bruno Ghyselen
  • Patent number: 11978627
    Abstract: A substrate for epitaxial growth includes a central region that has a center of the substrate and that serves as a non-modified region, and a peripheral region that surrounds the central region in a manner to be spaced apart from the center of the substrate by a distance and that serves as a modified region having a plurality of modified points. A method for manufacturing a substrate for epitaxial growth includes providing a substrate and forming a plurality of modified points in an interior of the substrate in position corresponding to the modified region. A semiconductor device including the substrate and a method for manufacturing the semiconductor device are also disclosed.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: May 7, 2024
    Assignee: Fujian Jing'an Optoelectronics Co., Ltd.
    Inventors: Juiping Li, Bohsiang Tseng, Jiahao Zhang, Mingxin Chen, Binbin Li, Yao Huo
  • Patent number: 11972986
    Abstract: Semiconductor wafers are produced by a process wherein a single-crystal ingot of semiconductor material is pulled and at least one wafer is removed from the ingot, wherein the wafer is subjected to a thermal treatment comprising a heat treatment step in which a radial temperature gradient acts on the wafer, wherein an analysis of the wafer of semiconductor material with respect to the formation of defects in the crystal lattice, so-called stress fields, is carried out.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: April 30, 2024
    Assignee: Siltronic AG
    Inventors: Michael Boy, Christina Kruegler
  • Patent number: 11967617
    Abstract: A nitride semiconductor substrate including a group III nitride semiconductor crystal and having a main surface, wherein a low index crystal plane is (0001) plane curved in a concave spherical shape to the main surface, and the off-angle (?m, ?a) at a position (x, y) in the main surface approximated by x representing a coordinate in a direction along <1-100> axis, y is a coordinate in a direction along <11-20> axis, (0, 0) represents a coordinate (x, y) of the center, ?m represents a direction component along <1-100> axis in an off-angle of <0001> axis with respect to a normal, ?a represents a direction component along <11-20> axis in the off-angle, (M1, A1) represents a rate of change in the off-angle (?m, ?a) with respect to the position (x, y) in the main surface, and (M2, A2) represents the off-angle (?m, ?a) at the center.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: April 23, 2024
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Fumimasa Horikiri, Takehiro Yoshida
  • Patent number: 11959191
    Abstract: A method for manufacturing a silicon single crystal wafer for a multilayer structure device including: using a silicon single crystal wafer with oxygen concentration of 12 ppma (JEITA) or higher and composing an NV region; and performing an RTA treatment in a nitrogen-containing atmosphere and a temperature of 1225° C. or higher, a mirror-polish processing treatment, and a BMD-forming heat treatment manufacturing a silicon single crystal wafer having at least a DZ layer with a thickness of 5 to 12.5 ?m and a BMD layer positioned immediately below the DZ layer and a BMD density of 1×1011/cm3 or higher from the silicon single crystal wafer surface. During device formation, the silicon wafer surface stress is absorbed immediately below a surface layer, distortion defects are absorbed by the BMD layer, device formation region strength is enhanced, and surface layer dislocation occurrence and extension is suppressed.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: April 16, 2024
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Wei Feng Qu, Shizuo Igawa
  • Patent number: 11958882
    Abstract: Disclosed herein are methods of preparing a composition comprising crystalline biomolecules, for example, crystalline antibodies. In exemplary embodiments, the method comprises forming a fluidized bed of crystalline biomolecules using, for example, a counter-flow centrifuge to exchange buffer and/or to concentrate the crystalline biomolecules in a solution. Also provided are methods of detecting crystalline biomolecules and/or amorphous biomolecules in a sample.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: April 16, 2024
    Assignee: AMGEN INC.
    Inventors: Rizwan Sharnez, William Trieu, Marc A. Caporini, Ron C. Kelly, Neill Burt, Laura Nicholson, Twinkle R. Christian
  • Patent number: 11952679
    Abstract: Inverse temperature crystallization processes are provided to produce perovskite single crystals (PSCs), as well as surface passivation techniques for producing stabilizing the PSCs in the bulk region. Stable hybrid perovskite material include a bulk region comprising a single crystal perovskite material having a first bandgap and a smooth perovskite surface layer having a second bandgap greater than the first bandgap. Devices for detection and energy conversion are also contemplated, including for spectroscopic photon and elementary particle detection, such as radiation detectors. Crystallization chambers for forming the PSCs are also provided.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: April 9, 2024
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Suneel Joglekar, Lingjie Jay Guo, Mark David Hammig
  • Patent number: 11946157
    Abstract: Methods and devices for epitaxially growing boron doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: April 2, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Rami Khazaka, Qi Xie
  • Patent number: 11948796
    Abstract: One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {100} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {110} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: April 2, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yi-Chiau Huang, Chen-Ying Wu, Abhishek Dube, Chia Cheng Chin, Saurabh Chopra
  • Patent number: 11946154
    Abstract: Provided are a dielectric material, a device including the dielectric material, and a method of preparing the dielectric material, in which the dielectric material may include: a layered perovskite compound, wherein the layered perovskite compound may include at least one selected from a Dion-Jacobson phase, an Aurivillius phase, and a Ruddlesden-Popper phase, a temperature coefficient of capacitance (TCC) of a capacitance at 200° C. with respect to a capacitance at 40° C. may be in a range of about ?15 percent (%) to about 15%, and a permittivity of the dielectric material may be 200 or greater in a range of about 1 kilohertz (kHz) to about 1 megahertz (MHz).
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: April 2, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyungjun Kim, Chan Kwak, Takayoshi Sasaki, Yasuo Ebina, Changsoo Lee, Dohwon Jung, Giyoung Jo, Takaaki Taniguchi
  • Patent number: 11939213
    Abstract: A structural molecular building block is provided and includes first structural molecules arranged in a three-dimensional structure and second structural molecules. Each of the second structural molecules is attached at a first region thereof to one of the first structural molecules to form the three-dimensional structure into a tessellating molecular building block and has a second region thereof for connection to a corresponding structural molecule of an additional tessellating molecular building block. The second structural molecules facilitate tessellation of the tessellating molecular building block with additional tessellating molecular building blocks to encourage growth of a macroscopic crystal.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 26, 2024
    Assignee: RAYTHEON COMPANY
    Inventors: Anthony Serino, Jacob Beal, Miles T. Rogers
  • Patent number: 11939267
    Abstract: A method and apparatus for producing AlN whiskers includes reduced incorporation of metal particles, an AlN whisker body, AlN whiskers, a resin molded body, and a method for producing the resin molded body. The method for producing AlN whiskers includes heating an Al-containing material in a material accommodation unit to thereby generate Al gas; and introducing the Al gas into a reaction chamber through a communication portion while introducing nitrogen gas into the reaction chamber through a gas inlet port, to thereby grow AlN whiskers on the surface of an Al2O3 substrate placed in the reaction chamber.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: March 26, 2024
    Assignee: NATIONAL UNIVERSITY CORPORATION NAGOYA UNIVERSITY
    Inventors: Toru Ujihara, Yukihisa Takeuchi, Daishi Shiojiri, Masaki Matsumoto, Hiroshi Saito, Ikuo Hayashi
  • Patent number: 11932964
    Abstract: A polycrystalline silicon material for producing silicon single crystal, containing a plurality of polycrystalline silicon chunks, in which assuming that a total concentration of donor elements present inside a bulk body of the polycrystalline silicon material is Cd1 [ppta], a total concentration of acceptor elements present inside the bulk body of the polycrystalline silicon material is Ca1 [ppta], a total concentration of the donor elements present on a surface of the polycrystalline silicon material is Cd2 [ppta], and a total concentration of the acceptor elements present on the surface of the polycrystalline silicon material is Ca2 [ppta], Cd1, Ca1, Cd2, and Ca2 satisfy a relation of 5 [ppta]?(Ca1+Ca2)?(Cd1+Cd2)?26 [ppta].
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: March 19, 2024
    Assignee: Tokuyama Coporation
    Inventors: Takuya Asano, Kouichi Saiki, Miki Emoto, Tooru Onoda
  • Patent number: 11932967
    Abstract: An object of the present invention is to provide a novel SiC single crystal with reduced internal stress while suppressing SiC sublimation. In order to solve the above problems, the present invention provides a method for producing SiC single crystals, including a stress reduction step of heating a SiC single crystal at 1800° C. or higher in an atmosphere containing Si and C elements to reduce internal stress in the SiC single crystal. With this configuration, the present invention can provide a novel SiC single crystal with reduced internal stress while suppressing SiC sublimation.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: March 19, 2024
    Assignees: KWANSEI GAKUIN EDUCATIONAL FOUNDATION, TOYOTA TSUSHO CORPORATION
    Inventor: Tadaaki Kaneko
  • Patent number: 11932961
    Abstract: An assembly sleeve of a single crystal pulling apparatus, and the single crystal pulling apparatus are provided. The assembly sleeve includes inner and outer cylinders and a bottom cylinder. The outer cylinder is provided with openings at both ends and sleeved onto the inner cylinder. The bottom cylinder is arranged at the opening at a lower end of the outer cylinder, and includes an annular plate and a lower cylinder. Each of the inner lower cylinders is of an inverted-cone shape, an upper end of the inner cylinder is connected to an upper end of the outer cylinder, an outer edge of the annular plate is hermetically connected to the lower end of the outer cylinder, an inner edge of the annular plate is connected to an upper end of the lower cylinder, and a lower end of the inner cylinder is fixedly connected to an upper surface of the annular plate.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: March 19, 2024
    Assignees: XIAN ESWIN MATERIAL TECHNOLOGY CO., LTD., XI'AN ESWIN SILICON WAFER TECHNOLOGY CO., LTD.
    Inventors: Wenwu Yang, Bokcheol Sim