Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.

Abstract: A method of manufacturing a thin film transistor array substrate to prevent damage to a pad is disclosed. The method includes forming gate lines and data lines that cross each other on a lower substrate, a gate insulating film located between the gate and data lines, a thin film transistor formed at every crossing, a lower gate pad electrode connected to the gate, and a lower data pad electrode; forming a passivation film on the substrate provided with the gate insulating film; forming a photo-resist pattern on the substrate provided with the passivation film; forming a first hole passing through a portion of the passivation film and a portion of the gate insulating film; removing the photo-resist pattern; forming a second hole exposing the lower gate pad electrode; and forming a transparent electrode pattern including an upper gate pad electrode connected to the exposed lower gate pad electrode.

Abstract: The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to decrease transient enhanced diffusion effects, minimize fixed pattern noise and fill factor loss.

Abstract: A method for forming a thin film transistor on a substrate is disclosed. A gate electrode and a gate insulation layer are disposed on a surface of the substrate. A deposition process is performed by utilizing hydrogen diluted silane to form a silicon-contained thin film on the gate insulation layer first. A hydrogen plasma etching process is thereafter performed. The deposition process and the etching process are repeated for at least one time to form an interface layer. Finally, an amorphous silicon layer, n+ doped Si layers, a source electrode, and a drain electrode are formed on the interface layer.

Abstract: A method of producing an optoelectronic substrate by detaching a thin layer from a semi-conducting nitride substrate and transferring it to an auxiliary substrate to provide at least one semi-conducting nitride layer thereon, metallizing at least a portion of the surface of the auxiliary substrate that includes the transferred nitride layer, bonding to a final substrate the metallized surface portion of the transferred nitrate layer of the auxiliary substrate, and removing the auxiliary substrate to provide an optoelectronic substrate comprising a semi-conducting nitride surface layer over a subjacent metallized portion and a supporting final substrate. Resultant optoelectronic substrates having low dislocation densities are also included.

Abstract: A method of fabricating an array substrate includes forming a buffer layer on a metal substrate, forming a thin film transistor including a gate electrode, a source electrode and a drain electrode on the buffer layer, forming a pixel electrode contacting the drain electrode, removing the metal substrate to expose a lower surface of the buffer layer, and forming a plastic material beneath the buffer layer such that the plastic material contacts the exposed lower surface of the buffer layer.

Abstract: Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.

Abstract: A method for fabricating a liquid crystal on silicon display device. The method includes providing a substrate, e.g., silicon wafer. The method includes forming a transistor layer overlying the substrate. Preferably, the transistor layer has a plurality of MOS devices therein. The method includes forming an interlayer dielectric layer (e.g., BPSG, FSG) overlying the transistor layer. The method includes planarizing the interlayer dielectric layer and forming a sacrificial layer (e.g., bottom antireflective coating, polymide, photoresist, polysilicon) overlying the planarized interlayer dielectric layer. The method includes forming a plurality of recessed regions within a portion of the interlayer dielectric layer through the sacrificial layer while other portions of the interlayer dielectric layer remain intact. Preferably, lithographic techniques are used for forming the recessed regions.

Abstract: A method for encapsulating a component by using a chamber in which there is a vacuum or controlled atmosphere, positioning a continuous sealing seam made of a metal or a metal alloy on a wettable surface previously placed on a substrate including at least one component and extending around the periphery of the component(s), positioning a package on the sealing seam, and raising the temperature inside the chamber to fuse the material that constitutes the sealing seam, thereby causing the package to drop onto the substrate and form a leaktight, hermetic seal between the package and the substrate.

Abstract: Disclosed is a packaged semiconductor device. The device includes a die with an active surface having a plurality of electrical contacts, a back surface located opposite the active surface, and a plurality of side surfaces. The device also includes a first light blocking protective coating that covers at least a portion of the side surfaces of the die. Also, disclosed is a semiconductor wafer including an active surface and a back surface, the active surface having a multiplicity of electrical contacts. The wafer includes a plurality of channels formed in the active surface of the wafer, the channels being arranged in a grid that effectively divide the wafer into a plurality of dice, each die having a plurality of the electrical contacts; and a light blocking filler material that fills the channels. Further, disclosed is a stamp suitable for applying a light blocking filler material into grooves on a semiconductor wafer.

Abstract: A CMOS image sensor and method for fabricating the same, wherein the CMOS image sensor has minimized dark current at the boundary area between a photodiode and an isolation layer. The present invention includes a first-conductivity-type doping area formed in the device isolation area of the substrate, the first-conductivity-type doping area surrounding the isolation area and a dielectric layer formed between the isolation layer and the first-conductivity-type doping area, wherein the first-conductivity-type doping area and the dielectric layer are located between the isolation layer and a second-conductivity-type diffusion area.

Abstract: The present invention relates to a method for keeping contact resistance of a pad low. The present invention also discloses a structure of the pad and a method for manufacturing the same, for use in circuit boards and LCD displays. The pad terminal comprises a first metal layer and a second metal layer covering the first metal layer. The second metal layer is removed before the pad terminal is deposited. Thus, the surface of the pad is clean and contact resistance is kept low, because there are no contaminants on the pad. Furthermore, the present invention discloses a pad having a raised part and a depressed part, enlarging the contact area of the pad. Therefore, contact resistance is reduced, and adhesion between the pad and the pad terminal is enhanced.

Abstract: A semiconductor device includes at least one semiconductor structure which has a plurality of external connection electrodes formed on a semiconductor substrate. An insulating sheet member is arranged on the side of the semiconductor structure. Upper interconnections have connection pad portions that are arranged on the insulating sheet member in correspondence with the upper interconnections and connected to the external connection electrodes of the semiconductor structure.

Abstract: Methods of fabricating silicon on insulator devices having the body-tied-to-source are described. In an embodiment, a method of forming a transistor device comprises: providing a semiconductor topography comprising a gate conductor spaced above a semiconductor layer by a gate dielectric, dielectric sidewall spacers adjacent to sidewalls of the gate conductor, and source and drain junctions laterally spaced apart by a body region in the semiconductor layer; and implanting metallic species in a bottom region of the semiconductor layer to form a conductive implant region to electrically connect the source junction to the body region.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are described. There is provided the semiconductor device including, a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a two-step gate electrode formed on the gate insulating layer, the two-step gate electrode having a first gate electrode layer formed on the gate insulating layer and a second gate electrode layer formed on the first gate electrode layer, the gate length of the second gate electrode layer being longer than that of the first gate electrode layer, extension regions formed in the semiconductor substrate to interpose a channel region of the semiconductor substrate beneath the second gate electrode layer, and source-drain regions formed in the outside of the extension regions toward the channel region, the source-drain regions adjoining the extension regions.

Abstract: A power amplifier includes a substrate, a heat sink for dissipating heat, and a heterojunction bipolar transistor (HBT) disposed on the substrate. The HBT includes a collector, a base, and at least an emitter. The power amplifier further includes an emitter electrode directly connecting the heat sink and the emitter of the HBT. The emitter electrode is a flip-chip bump, and the heat sink is a metal layer that sandwiches the HBT with the substrate. Alternatively, the emitter electrode is a backside via that penetrates the substrate, and the heat sink is a metal layer, disposed on the substrate opposite the HBT.

Abstract: The present invention relates to a liquid crystal display panel and a fabricating method thereof that is capable of enhancing crystallization efficiency of an active layer and simplifying the fabricating process. A fabricating method of a liquid crystal display panel includes forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode formed thereon; forming an amorphous silicon film on the gate insulating film; forming an insulating pattern on the amorphous silicon film; crystallizing the amorphous silicon film into a polycrystalline silicon film using a derivative metal, the polycrystalline silicon film having source, drain and channel areas, wherein the insulating pattern overlaps the channel area of the polycrystalline silicon film; and forming source and drain electrodes on the polycrystalline silicon film, wherein the source and the drain electrodes contacting the source and drain areas of the polycrystalline silicon film, respectively.

Abstract: The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to decrease transient enhanced diffusion effects, minimize fixed pattern noise and fill factor loss.

Abstract: A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate.

Abstract: The present invention provides a process of manufacturing a semiconductor device 200 while reducing silicon loss. In one aspect, the process includes removing a photoresist layer 270 from a semiconductor substrate 235 adjacent a gate 240 and cleaning the semiconductor substrate with a wet clean solution. The removing step includes subjecting the photoresist layer 270 to a plasma ash. The plasma ash removes at least a portion of a crust 275 formed on the photoresist layer 270 but leaves a substantial portion of the photoresist layer 270. The photoresist layer 270 is subjected to a wet etch subsequent to the plasma ash that removes a substantial portion of the photoresist layer 270.