Abstract: A connection establishment method includes a terminal device obtaining historical data of a multipath transmission control protocol (MPTCP) connection established between the terminal device and an application server. The historical data includes a data transmission delay of a transmission control protocol (TCP) connection corresponding to a Wi-Fi network and a data transmission delay of a TCP connection corresponding to a cellular network. The terminal device determines, based on the historical data, that the data transmission delay of the TCP connection corresponding to the cellular network is less than or equal to the data transmission delay of the TCP connection corresponding to the Wi-Fi network, and establishes a first TCP connection to the application server through an interface of the cellular network; and after the first TCP connection is successfully established, the terminal device establishes a second TCP connection to the application server through an interface of the Wi-Fi network.

Abstract: Provided is a method for processing images. The method includes: acquiring a plurality of original sub-images acquired by a plurality of cameras in a camera array; converting first pixel coordinates of each pixel in each original sub-image in an image coordinate system into target pixel coordinates in a target plane coordinate system; determining a region pixel value of each sub-region according to a correspondence between the target pixel coordinates of each pixel in each original sub-image and each sub-region in the target plane; and determining a spliced image in the target plane based on the region pixel value of each sub-region.

Abstract: A testing device for testing an integrated circuit package is provided, including a printed circuit board, a testing socket, a conductive fastener, a cover, and a conductive element assembly. The printed circuit board includes a first metal layer formed on the bottom surface thereof. The testing socket is disposed above the printed circuit board. The conductive fastener is configured to secure the testing socket to the printed circuit board, wherein the conductive fastener is electrically connected to the first metal layer and the testing socket. The cover is disposed above the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket, wherein the cover makes electrical contact with the integrated circuit package. The conductive element assembly is disposed between and electrically connected to the cover and the testing socket.

Abstract: A package structure includes a first semiconductor die, a first insulating encapsulation, a thermal coupling structure, and a heat dissipating component thermally coupled to the first semiconductor die through the thermal coupling structure. The first semiconductor die includes an active side, a rear side, and a sidewall connected to the active side and the rear side. The first insulating encapsulation extends along the sidewall of the first semiconductor die and includes a first side substantially leveled with the active side, a second side opposite to the first side, and topographic features at the second side. The thermal coupling structure includes a metallic layer overlying and the rear side of the first semiconductor die and the topographic features of the first insulating encapsulation. A manufacturing method of a package structure is also provided.

Abstract: A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

Abstract: Disclosed is a multi-layered composite bionic self-retaining prosthesis for a femoral shaft, including a scaffold, an upper bone plate, and a lower bone plate. An upper outer side of the scaffold is fixed to a low inner side of the upper bone plate, and a lower outer side of the scaffold is fixed to an upper inner side of the lower bone plate. The scaffold includes an upper trabeculae layer, a middle cortical bone layer and a lower trabeculae layer. The middle cortical bone layer is a multi-layered composite structure which includes an outer frame layer, a middle filling layer and an inner frame layer. The upper and lower bone plates each include an inner trabeculae layer and an outer reinforcement layer.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Abstract: An alignment mark includes a first alignment marker located on a first surface of a substrate and a second alignment marker located on a second surface of the substrate. The second alignment marker is arranged to be matched with the first alignment marker, and capable of representing a process variation between the second alignment marker and the first alignment marker.

Abstract: A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.

Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.

Abstract: Disclosed are a display panel, a control method for the same, and a display device. The display panel includes: M rows and N columns of pixel units, N current data lines sequentially arranged along a row direction, and N time-length data lines sequentially arranged along the row direction. Each pixel unit includes a pixel circuit, the pixel circuit including a current data terminal and a time-length data terminal. An ith column of the current data lines and an ith column of the time-length data lines are respectively located on two sides of an ith column of pixel units, the current data terminals of the pixel circuits of the ith column of pixel units are electrically connected to the ith column of the current data lines.

Abstract: Provided is a pixel circuit. The pixel circuit includes a reset circuit, a data write circuit, a light-emission control circuit, and a drive circuit; wherein the reset circuit is configured to transmit a reset power signal supplied by the reset power terminal to the first node in response to a reset control signal; the data write circuit is configured to transmit a data signal supplied by the data signal terminal to the first node in response to a gate drive signal; the light-emission control circuit is configured to control conduction/non-conduction between the cathode of the light-emitting element and the second node, and control conduction/non-conduction between the third node and the pull-down power terminal, in response to a light-emission control signal; and the drive circuit is configured to control conduction/non-conduction between the second node and the third node in response to a potential of the first node.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a first base portion and a second base portion, an isolation feature sandwiched between the first base portion and the second base portion, a center dielectric fin over the isolation feature, a first anti-punch-through (APT) feature over the first base portion, a second APT feature over the second base portion, a first stack of channel members over the first APT feature, and a second stack of channel members over the second APT feature. The center dielectric fin is sandwiched between the first stack of channel members and the second stack of channel members as well as between the first APT feature and the second APT feature.

Abstract: An apparatus for monitoring sleep quality includes a plurality of sensors, a plurality of actuator modules, a transceiver, and a processor operatively coupled with the plurality of sensor modules, the plurality of actuator modules, and the transceiver. The processor is configured to monitor a sleep session of a user utilizing the apparatus. To monitor the sleep session, the processor is further configured to monitor a sleep state of the user, monitor a sleep stage of the user, and monitor a sleep condition. The processor is further configured to select a sleep facilitating action, control the sleep facilitating action based on the monitoring, and collect data related to the sleep session, and update a sleep history database associated with the user based on the data related to the sleep session.

Abstract: A micro inverter, a photovoltaic system and a method for controlling a micro inverter are provided. The micro inverter includes a controller, a primary H-bridge, a transformer, a bi-directional switch arm and a capacitor arm. The controller is configured to: determine a reactive current based on a grid voltage, an equivalent capacitance of an output terminal of the inverter and a grid angle; add the reactive current to a given current to generate an internal phase-shift angle and an external phase-shift angle from a new given current obtained through the addition, where the internal phase-shift angle refers to a phase-shift angle between two arms of the primary H-bridge and the external phase-shift angle refers to a phase-shift angle between the primary H-bridge and the bi-directional switch arm.

Abstract: A computer fan includes a base frame, a fan blade body, and a positioning device. A base plate is arranged on the base frame. A shaft is arranged on the base plate. A through hole is arranged at a central position of the fan blade body for being sleeved on the shaft. The positioning device is for coupling to a top of the shaft, such that the fan blade body is located under the positioning device, and the positioning device is capable of being stabilized and rest on the shaft when the fan blade body is rotating relative to the shaft.

Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.

Abstract: The present disclosure provides compounds having Formula I: and the pharmaceutically acceptable salts and solvates thereof, wherein variables are as defined as set forth in the specification. The present disclosure also provides compounds of Formula I for use to treat a disease, disorder, or condition responsive to Bcl-2 protein inhibition, particularly Bcl-2 WT and/or Bcl-2 G101V.

Abstract: A high-nickel ternary core-shell precursor for a lithium battery, a positive electrode material and a preparation method therefor. The chemical structural formula of the precursor is zNi(C4H7N2O2)2—Nix-zM1yM21-x-y(OH)2, wherein M1 and M2 are two of cobalt, aluminum, and manganese. The preparation method comprises: pumping a prepared metal salt solution, a dimethylglyoxime-ammonia water composite solution, and an ammonia water solution into a reaction kettle, maintaining the pH of a reaction system, and controlling the reaction time to obtain a sphere-like precursor inner core with a structural formula of Ni(C4H7N2O2)2; pumping the metal salt solution and the ammonia water solution, stopping pumping the dimethylglyoxime-ammonia water composite solution, pumping a sodium hydroxide solution to obtain a sphere-like core-shell precursor, washing, drying, sieving and deironing the precursor, mixing with a lithium source, and calcining to prepare the positive electrode material.