Abstract: A lifting device for lifting and holding a small watercraft in a fixed position and that includes a support structure and a lifting mechanism. The support structure supports the lifting mechanism in a body of water, usually with some form of flotation device. The lifting mechanism is movable between a raised position that holds the watercraft steady and in a fixed position and a lowered position in which the watercraft is floating in the water. A handle bar assembly allows a user to maneuver the lifting mechanism between the positions.

Abstract: A lifting device for lifting and holding a small watercraft in a fixed position and that includes a support structure and a lifting mechanism. The support structure supports the lifting mechanism in a body of water, usually with some form of flotation device. The lifting mechanism is movable between a raised position that holds the watercraft steady and in a fixed position and a lowered position in which the watercraft is floating in the water. A handle bar assembly allows a user to maneuver the lifting mechanism between the positions.

Abstract: A method of reducing a set of instructions for execution on a processor extracts information from a first instruction of the set of instructions. The method identifies unencoded space in one or more further instructions of the set of instructions and replaces the unencoded space of the one or more further instructions with the extracted information of the first instruction so as to form one or more amalgamated instructions. The method removes the first instruction from the set of instructions. A method of expanding a set of reduced instructions on a processor is also disclosed.

Abstract: A method of executing an instruction set having a first instruction and a second instruction, includes: reading the first instruction; determining whether the first instruction is integral with the second instruction; reading the second instruction; when the first instruction is integral with the second instruction, interpreting a first operator field of the second instruction to represent a first operator; and when the first instruction is not integral with the second instruction, interpreting the first operator field of the second instruction to represent a second operator, wherein the first operator is different to the second operator.

Abstract: A method of encapsulating a long instruction in a set of short instructions for execution on a processor, the long instruction having k bits and each short instruction having l bits where l<k, includes assembling a first portion of the long instruction and a first identifier to form a first instruction of the set of short instructions; and assembling a second portion of the long instruction and a second identifier to form a second instruction of the set of short instructions; wherein at least one of the first and second identifiers is for identifying to the processor that the set of short instructions encapsulates the long instruction.

Abstract: A method of executing an instruction set to select a set of registers, includes reading a first instruction of the instruction set; interpreting a first operand of the first instruction to represent a first register S to be selected; interpreting a second operand of the first instruction to represent a number N of registers to be selected; and selecting N consecutive registers starting at the first register S to form the set of registers.

Abstract: The present invention provides a communications unit for operation in a communication system in accordance with a protocol that operates to a first clock resolution, the communications unit comprising a first clock, operating to the first resolution, a second clock operating to a second resolution higher than the first resolution, means configured to respond to a request to report a clock value by reporting: (a) the current value of the first clock and (b) information indicating the time on the second clock at which the first clock ticked to its current value.

Abstract: A method of executing an instruction set including a first instruction and a second instruction, includes reading the first instruction; determining whether the first instruction is an instruction which is integral with the second instruction; reading the second instruction; if the first instruction is integral with the second instruction, interpreting the operand field of the second instruction to indicate at least one value to be used in conjunction with at least one bit of the first instruction; and if the first instruction is not integral with the second instruction, interpreting the operand field of the second instruction to indicate an entry of a look-up table.

Abstract: The present invention provides a communications unit for operation in a communication system in accordance with a protocol that operates to a first clock resolution, the communications unit comprising a first clock, operating to the first resolution, a second clock operating to a second resolution higher than the first resolution, means configured to respond to a request to report a clock value by reporting: (a) the current value of the first clock and (b) information indicating the time on the second clock at which the first clock ticked to its current value.

Abstract: A method of mixing and transmitting encoded media data, wherein the data is decoded, mixed and recorded only when mixing with other data is required. When no mixing is required the encoded data is transmitted directly. In further methods, two sets of media data may be transmitted to an output device for mixing and outputting.

Abstract: A method of executing an instruction set to select a set of registers, includes reading a first instruction of the instruction set; interpreting a first operand of the first instruction to represent a first register S to be selected; interpreting a second operand of the first instruction to represent a number N of registers to be selected; and selecting N consecutive registers starting at the first register S to form the set of registers.

Abstract: A method of reducing a set of instructions for execution on a processor, the method comprising: extracting information from a first instruction of the set of instructions; identifying unencoded space in one or more further instructions of the set of instructions; replacing the unencoded space of the one or more further instructions with the extracted information of the first instruction so as to form one or more amalgamated instructions; and removing the first instruction from the set of instructions.

Abstract: A method of executing an instruction set having a first instruction and a second instruction, includes: reading the first instruction; determining whether the first instruction is integral with the second instruction; reading the second instruction; if the first instruction is integral with the second instruction, interpreting a first operator field of the second instruction to represent a first operator; and if the first instruction is not integral with the second instruction, interpreting the first operator field of the second instruction to represent a second operator, wherein the first operator is different to the second operator.

Abstract: A method of encapsulating a long instruction in a set of short instructions for execution on a processor, the long instruction having k bits and each short instruction having l bits where l<k, includes assembling a first portion of the long instruction and a first identifier to form a first instruction of the set of short instructions; and assembling a second portion of the long instruction and a second identifier to form a second instruction of the set of short instructions; wherein at least one of the first and second identifiers is for identifying to the processor that the set of short instructions encapsulates the long instruction.

Abstract: The present invention provides a communications unit for operation in a communication system in accordance with a protocol that operates to a first clock resolution, the communications unit comprising a first clock, operating to the first resolution, a second clock operating to a second resolution higher than the first resolution, means configured to respond to a request to report a clock value by reporting: (a) the current value of the first clock and (b) information indicating the time on the second clock at which the first clock ticked to its current value.

Abstract: A method of executing an instruction set including a first instruction and a second instruction, includes reading the first instruction; determining whether the first instruction is an instruction which is integral with the second instruction; reading the second instruction; if the first instruction is integral with the second instruction, interpreting the operand field of the second instruction to indicate at least one value to be used in conjunction with at least one bit of the first instruction; and if the first instruction is not integral with the second instruction, interpreting the operand field of the second instruction to indicate an entry of a look-up table.

Abstract: A method of mixing and transmitting encoded media data, wherein the data is decoded, mixed and recorded only when mixing with other data is required. When no mixing is required the encoded data is transmitted directly. In further methods, two sets of media data may be transmitted to an output device for mixing and outputting.

Abstract: A combination of a 5HT1B/1D agonist and a COX-2 selective inhibitor is useful in the treatment and or prevention of migraine.

Abstract: A combination of a 5HT1B/1D agonist and a COX-2 selective inhibitor is useful in the treatment and or prevention of migraine.

Abstract: A combination of a 5HT1B/1D agonist and a COX-2 selective inhibitor is useful in the treatment and or prevention of migraine.