Abstract: The images sensor includes a readout circuit capacitatively coupled to a memory circuit. The readout circuit includes: (i) a photon detector to receive a plurality of photons and to provide a charge signal corresponding to the received photons, (ii) a resettable integrator that is reset multiple times over a single exposure time and provides an analog representation of the incident photons during the last integration cycle, and (iii) a comparator that monitors the integrator output and generates a reset pulse when the integrator reaches a built-in threshold value. The memory circuit includes: (i) a receiver circuit that detects the output of the digital driver in the front-end readout circuit via capacitive coupling and generates a digital voltage pulse for each received signal, and (ii) a digital counting memory to count the received pulses to provide a coarse digital representation of how many times the integrator is reset.

Abstract: The images sensor includes a readout circuit capacitatively coupled to a memory circuit. The readout circuit includes: (i) a photon detector to receive a plurality of photons and to provide a charge signal corresponding to the received photons, (ii) a resettable integrator that is reset multiple times over a single exposure time and provides an analog representation of the incident photons during the last integration cycle, and (iii) a comparator that monitors the integrator output and generates a reset pulse when the integrator reaches a built-in threshold value. The memory circuit includes: (i) a receiver circuit that detects the output of the digital driver in the front-end readout circuit via capacitive coupling and generates a digital voltage pulse for each received signal, and (ii) a digital counting memory to count the received pulses to provide a coarse digital representation of how many times the integrator is reset.

Abstract: A vertical electrical device includes a region in a substrate extending from a surface of the substrate, the region having an inner wall and an outer wall circumscribing the inner wall. An inner electrically conductive layer is disposed on the inner wall and an outer electrically conductive layer is disposed on the outer wall, with an electrically insulative material disposed between the inner and outer layers. An electrical conductor in the substrate is bounded by the inner electrically conductive layer.

Abstract: A two dimensional time delay integration CMOS image sensor having a plurality of pinned photodiodes, each pinned photodiode collects a charge when light strikes the pinned photodiode, a plurality of electrodes separating the plurality of pinned photodiodes, the plurality of electrodes are configured for two dimensional charge transport between two adjacent pinned photodiodes, and a plurality of readout nodes connected to the plurality of pinned photodiodes via address lines.

Abstract: A correlated double sampling circuit and method for providing the same are disclosed. The circuit may include an amplifier, a plurality of capacitors, and a switch matrix. The amplifier provides a reset voltage replica and a signal voltage replica. The switch matrix controls a plurality of switches to perform correlated double sampling over at least three phases. The first phase for sampling the reset voltage replica on a first and second capacitors. The second phase for sampling the reset voltage replica and the kTC noise on a third capacitor. The first phase producing a thermal kTC noise from the first and second capacitors. The third phase for subtracting a charge representing the signal voltage replica, the kTC noise and the reset voltage replica, combined, from the charge sampled in the second phase to provide an output voltage. The method for providing low noise correlated double sampling includes controlling the plurality of switches to provide the at least three phases.

Abstract: A through-wafer via interconnect region is in a circuit portion of a wafer, the circuit portion including at least one electrically conducting metal layer and configured for use, after dicing of the wafer, as one of a plurality of layers stacked vertically to form a three dimensional integrated circuit. Within the metal layer in the circuit portion, the metal is removeably distributed such that the ratio of metal to nonmetal area, within the via region, varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region.

Abstract: The images sensor includes a readout circuit capacitatively coupled to a memory circuit. The readout circuit includes: (i) a photon detector to receive a plurality of photons and to provide a charge signal corresponding to the received photons, (ii) a resettable integrator that is reset multiple times over a single exposure time and provides an analog representation of the incident photons during the last integration cycle, and (iii) a comparator that monitors the integrator output and generates a reset pulse when the integrator reaches a built-in threshold value. The memory circuit includes: (i) a receiver circuit that detects the output of the digital driver in the front-end readout circuit via capacitive coupling and generates a digital voltage pulse for each received signal, and (ii) a digital counting memory to count the received pulses to provide a coarse digital representation of how many times the integrator is reset.

Abstract: A three dimensional integrated circuit and method for making the same. The three dimensional integrated circuit has a first and a second active circuit layers with a first metal layer and a second metal layer, respectively. The metal layers are connected by metal inside a buried via. The fabrication method includes etching a via in the first active circuit layer to expose the first metal layer without penetrating the first metal layer, depositing metal inside the via, the metal inside the via being in contact with the first metal layer, and bonding the second active circuit layer to the first active circuit layer using a metal bond that connects the metal inside the via to the second metal layer of the second active circuit layer.

Abstract: An imaging system includes a row and column array of active pixels, each having an associated pitch. In response to respective control signals, each pixel outputs a reset level which includes noise components, or a signal level which includes signal and noise components. Multiple column buffers, each having a pitch equal to or less than that of a pixel, convey the outputs of respective pixel columns to a bus line. Each buffer comprises ‘odd’ and ‘even’ S&H/CDS circuits, which process the pixel outputs of odd and even rows, respectively. Each S&H/CDS circuit subtracts pixel reset level from signal level to produce an output in which correlated noise is suppressed. Each column buffer includes a buffer amplifier which conveys the output to the bus line. A gain amplifier separate from the column buffers is coupled to the bus line such that it amplifies the outputs of a multiple column buffers.

Abstract: A three dimensional integrated circuit and method for making the same. The three dimensional integrated circuit has a first and a second active circuit layers with a first metal layer and a second metal layer, respectively. The metal layers are connected by metal inside a buried via. The fabrication method includes etching a via in the first active circuit layer to expose the first metal layer without penetrating the first metal layer, depositing metal inside the via, the metal inside the via being in contact with the first metal layer, and bonding the second active circuit layer to the first active circuit layer using a metal bond that connects the metal inside the via to the second metal layer of the second active circuit layer.

Abstract: The images sensor includes a readout circuit capacitatively coupled to a memory circuit. The readout circuit includes: (i) a photon detector to receive a plurality of photons and to provide a charge signal corresponding to the received photons, (ii) a resettable integrator that is reset multiple times over a single exposure time and provides an analog representation of the incident photons during the last integration cycle, and (iii) a comparator that monitors the integrator output and generates a reset pulse when the integrator reaches a built-in threshold value. The memory circuit includes: (i) a receiver circuit that detects the output of the digital driver in the front-end readout circuit via capacitive coupling and generates a digital voltage pulse for each received signal, and (ii) a digital counting memory to count the received pulses to provide a coarse digital representation of how many times the integrator is reset.

Abstract: An adaptive low noise offset subtraction pixel and method for adaptive low noise offset subtraction is disclosed. The pixel has a photosensitive element, a current offset memorization circuit and a current subtraction circuit. The current subtraction circuit coupled to the current offset memorization circuit, and comprises a transistor selected from a group consisting of a junction gate field-effect transistor, a bipolar transistor, a MOSFET transistor with a spiral channel, and a MOSFET transistor with a buried channel. The transistor configured to receive an offset current from the current offset memorization circuit and subtract the offset current from an output signal current received from the photosensitive element to provide an offset-free signal current and a shot noise limited subtraction current.

Abstract: A correlated double sampling circuit and method for providing the same are disclosed. The circuit may include an amplifier, a plurality of capacitors, and a switch matrix. The amplifier provides a reset voltage replica and a signal voltage replica. The switch matrix controls a plurality of switches to perform correlated double sampling over at least three phases. The first phase for sampling the reset voltage replica on a first and second capacitors. The second phase for sampling the reset voltage replica and the kTC noise on a third capacitor. The first phase producing a thermal kTC noise from the first and second capacitors. The third phase for subtracting a charge representing the signal voltage replica, the kTC noise and the reset voltage replica, combined, from the charge sampled in the second phase to provide an output voltage. The method for providing low noise correlated double sampling includes controlling the plurality of switches to provide the at least three phases.

Abstract: A three dimensional integrated circuit and method for making the same. The three dimensional integrated circuit has a first and a second active circuit layers with a first metal layer and a second metal layer, respectively. The metal layers are connected by metal inside a buried via. The fabrication method includes etching a via in the first active circuit layer to expose the first metal layer without penetrating the first metal layer, depositing metal inside the via, the metal inside the via being in contact with the first metal layer, and bonding the second active circuit layer to the first active circuit layer using a metal bond that connects the metal inside the via to the second metal layer of the second active circuit layer.

Abstract: An imaging system includes a row and column array of active pixels, each having an associated pitch. In response to respective control signals, each pixel outputs a reset level which includes noise components, or a signal level which includes signal and noise components. Multiple column buffers, each having a pitch equal to or less than that of a pixel, convey the outputs of respective pixel columns to a bus line. Each buffer comprises ‘odd’ and ‘even’ S&H/CDS circuits, which process the pixel outputs of odd and even rows, respectively. Each S&H/CDS circuit subtracts pixel reset level from signal level to produce an output in which correlated noise is suppressed. Each column buffer includes a buffer amplifier which conveys the output to the bus line. A gain amplifier separate from the column buffers is coupled to the bus line such that it amplifies the outputs of a multiple column buffers.

Abstract: A backside illuminated CMOS image sensor having an silicon layer with a front side and a backside, the silicon layer liberates charge when illuminated from the backside with light, an active pixel circuitry located on the front side of the semiconductor layer, a pinned photodiode adjacent to the active pixel circuitry on the front side of the semiconductor layer and configured to collect charge liberated in the semiconductor layer, and an implant located in the semiconductor layer, underneath the active pixel circuitry, for allowing charge liberated in the semiconductor layer to drift from the backside of the semiconductor layer to the pinned photodiode on the front side of the semiconductor layer.

Abstract: A through-wafer via interconnect region is in a circuit portion of a wafer, the circuit portion including at least one electrically conducting metal layer and configured for use, after dicing of the wafer, as one of a plurality of layers stacked vertically to form a three dimensional integrated circuit. Within the metal layer in the circuit portion, the metal is removably distributed such that the ratio of metal to nonmetal area, within the via region, varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region.

Abstract: A detector circuit having an integration capacitor coupled to an amplifier via a switch matrix and a comparator coupled to the amplifier, the integration capacitor operable in two or more phases, the switch matrix is configured to phase switch the integration capacitor, the comparator triggers the phase switch when the output voltage of the amplifier passes the threshold voltage of the comparator.

Abstract: A backside illuminated CMOS image sensor having an silicon layer with a front side and a backside, the silicon layer liberates charge when illuminated from the backside with light, an active pixel circuitry located on the front side of the semiconductor layer, a pinned photodiode adjacent to the active pixel circuitry on the front side of the semiconductor layer and configured to collect charge liberated in the semiconductor layer, and an implant located in the semiconductor layer, underneath the active pixel circuitry, for allowing charge liberated in the semiconductor layer to drift from the backside of the semiconductor layer to the pinned photodiode on the front side of the semiconductor layer.

Abstract: A detector circuit having an integration capacitor coupled to an amplifier via a switch matrix and a comparator coupled to the amplifier, the integration capacitor operable in two or more phases, the switch matrix is configured to phase switch the integration capacitor, the comparator triggers the phase switch when the output voltage of the amplifier passes the threshold voltage of the comparator.