Abstract: An engine malfunction determination system includes a vehicle engine, an engine sensor system, an engine control module and an electronic display device. The engine sensor system has at least one sensor configured to detect an operation condition of the vehicle engine. The engine control module is in electrical communication with the sensor system to receive a detection signal from the engine sensor system regarding the operation condition of the vehicle engine. The engine control module is programmed to determine an anomaly in the detection signal. The electronic display device is programmed to display an indication of engine malfunction when the engine control module determines that the anomaly in the detection signal exceeds a predetermined threshold.

Abstract: Provided is a liquid crystal panel. The liquid crystal panel includes a glass substrate, a black matrix and a common electrode which are sequentially stacked. The common electrode completely covers the black matrix. The black matrix comprises a plurality of rows of first shading lines and a plurality of rows of second shading lines. The first shading lines and the second shading lines are perpendicular to and intersect with each other. The glass substrate is further provided with a first signal source located on one side of the black matrix and a plurality of rows of first metal lines disposed on one side facing away from the glass substrate to connect the first signal source and the first metal lines of the common electrode. The first metal lines covering the first shading lines replace common lines located outside the display area of the array substrate.

Abstract: Disclosed is a GOA circuit, including GOA units, which are cascade coupled. An nth stage GOA unit charges nth stage, n+1th stage and n+2th stage horizontal scanning lines. The nth stage GOA unit includes a pull-up control circuit, receiving a start signal CT and outputting a pull-up control signal Q(n); a pull-up circuit, receiving Q(n), an nth stage clock signal CK(n), an n+1th stage clock signal CK(n+1) and an n+2th stage clock signal CK(n+2), and outputting an nth stage transfer signal ST(n), an nth stage scan driving signal G(n), an n+1th stage scan driving signal G(n+1) and an n+2th stage scan driving signal G(n+2); a pull-down circuit, receiving an n+6th stage scan driving signal G(n+6) and a first direct current low voltage signal VSSQ1 to enable Q(n) in an off state. Three stages scan driving signals can be outputted through one stage GOA unit.

Abstract: The present disclosure relates to a liquid crystal display (LCD) having a substrate and at least one scanning controller. the substrate is configured with a plurality of thin film transistors (TFTs). Each of the TFTs includes a gate, a drain and a pixel electrode, and the gate of each of the TFTs electrically connecting to the scanning controller along a first direction in sequence. One end of the drain connects to the pixel electrode, and the other end of the drain is stacked on the gate along a third direction perpendicular to the substrate. The drain is insulated from the gate, and a dimension of a projection area of the drain on the gate along the third direction increases when a distance between the TFT and the scanning controller in the first direction increases.

Abstract: The embodiment of the present invention provides an electrostatic discharge unit, wherein the electrostatic discharge unit is located an array substrate of a liquid crystal display panel, and comprising: a first branch including at least one first dual gate thin film transistor; a second branch including at least one second dual gate thin film transistor; wherein the first branch and the second branch are connected in parallel, a common first end point is electrically connected to a protection circuit, a common second end point is electrically connected to a common electrode line, and conduction directions of the first dual gate thin film transistor and the second dual gate thin film transistor are opposite. The embodiment of the invention also discloses an array substrate and a liquid crystal display panel. The invention has the advantages of facilitating the realization of the narrow frame of the liquid crystal display panel.

Abstract: The GOA circuit includes multiple cascaded GOA units. An (n)th GOA unit includes pull-up control circuit, pull-up circuit, pull-down circuit, first pull-down holding circuit, and second pull down holding circuit. The pull-up control circuit receives an activation signal CT, and outputs a pull-up control signal Q(n). The pull-up circuit receives Q(n) and a first clock signal CK, and outputs an (n)th cascade signal ST(n) and an (n)th scan signal G(n). The pull-down circuit receives an (n+4)th cascade signal ST(n+4), a first DC low-voltage signal VSSG1, and a second DC low-voltage signal VSSQ2, and keeps Q(n) and G(n) at a turn-off state. The first pull-down holding circuit receives CK, ST(n), VSSG1, and VSSQ2, and keeps Q(n) and G(n) at the turn-off state. The second pull down holding circuit receives a second clock signal XCK, an (n?4)th cascade signal ST(n?4), and VSSG1, and keeps Q(n) and G(n) at the turn-off state.

Abstract: The GOA circuit includes multiple cascaded GOA units. An (n)th GOA unit includes pull-up control circuit, pull-up circuit, pull-down circuit, first pull-down holding circuit, and second pull down holding circuit. The pull-up control circuit receives an activation signal CT, and outputs a pull-up control signal Q(n). The pull-up circuit receives Q(n) and a first clock signal CK, and outputs an (n)th cascade signal ST(n) and an (n)th scan signal G(n). The pull-down circuit receives an (n+4)th cascade signal ST(n+4), a first DC low-voltage signal VSSG1, and a second DC low-voltage signal VSSQ2, and keeps Q(n) and G(n) at a turn-off state. The first pull-down holding circuit receives CK, ST(n), VSSG1, and VSSQ2, and keeps Q(n) and G(n) at the turn-off state. The second pull down holding circuit receives a second clock signal XCK, an (n?4)th cascade signal ST(n?4), and VSSG1, and keeps Q(n) and G(n) at the turn-off state.

Abstract: Disclosed are a GOA circuit and a liquid crystal display device. The GOA circuit includes multiple stages of GOA sub-circuits connected in cascade. In a pull-down unit of a GOA sub-circuit, a first thin film transistor and a second thin film transistor are connected in series. Leakage current at Q point in the GOA circuit can be reduced, stability of the GOA circuit can be improved in harsh environments, and reliability of a liquid crystal panel can be enhanced.

Abstract: A display panel includes a first metal layer and a second metal layer sequentially stacked. The first metal layer includes a plurality of first metal lines and first gaps arranged between the first metal lines. The second metal layer includes a plurality of second metal lines arranged in a spaced manner. The second metal lines have an extension direction that is identical to an extension direction of the first metal lines. The second metal lines and the first metal lines are arranged to stagger, in position, with respect to each other. The second metal lines have orthogonal projections on the first metal layer that are located in areas of the first gaps in order to prevent shorting between the second metal lines in a process of manufacturing the second metal lines. A method for manufacturing the display panel and a display device are also provided.

Abstract: Disclosed is a GOA circuit, including GOA units, which are cascade coupled. An nth stage GOA unit charges nth stage, n+1th stage and n+2th stage horizontal scanning lines. The nth stage GOA unit includes a pull-up control circuit, receiving a start signal CT and outputting a pull-up control signal Q(n); a pull-up circuit, receiving Q(n), an nth stage clock signal CK(n), an n+1th stage clock signal CK(n+1) and an n+2th stage clock signal CK(n+2), and outputting an nth stage transfer signal ST(n), an nth stage scan driving signal G(n), an n+1th stage scan driving signal G(n+1) and an n+2th stage scan driving signal G(n+2); a pull-down circuit, receiving an n+6th stage scan driving signal G(n+6) and a first direct current low voltage signal VSSQ1 to enable Q(n) in an off state. Three stages scan driving signals can be outputted through one stage GOA unit.

Abstract: Provided is a liquid crystal panel. The liquid crystal panel includes a glass substrate, a black matrix and a common electrode which are sequentially stacked. The common electrode completely covers the black matrix. The black matrix comprises a plurality of rows of first shading lines and a plurality of rows of second shading lines. The first shading lines and the second shading lines are perpendicular to and intersect with each other. The glass substrate is further provided with a first signal source located on one side of the black matrix and a plurality of rows of first metal lines disposed on one side facing away from the glass substrate to connect the first signal source and the first metal lines of the common electrode. The first metal lines covering the first shading lines replace common lines located outside the display area of the array substrate.

Abstract: The present disclosure relates to a liquid crystal display (LCD) having a substrate and at least one scanning controller. the substrate is configured with a plurality of thin film transistors (TFTs). Each of the TFTs includes a gate, a drain and a pixel electrode, and the gate of each of the TFTs electrically connecting to the scanning controller along a first direction in sequence. One end of the drain connects to the pixel electrode, and the other end of the drain is stacked on the gate along a third direction perpendicular to the substrate. The drain is insulated from the gate, and a dimension of a projection area of the drain on the gate along the third direction increases when a distance between the TFT and the scanning controller in the first direction increases.

Abstract: A display panel includes a first metal layer and a second metal layer sequentially stacked. The first metal layer includes a plurality of first metal lines and first gaps arranged between the first metal lines. The second metal layer includes a plurality of second metal lines arranged in a spaced manner. The second metal lines have an extension direction that is identical to an extension direction of the first metal lines. The second metal lines and the first metal lines are arranged to stagger, in position, with respect to each other. The second metal lines have orthogonal projections on the first metal layer that are located in areas of the first gaps in order to prevent shorting between the second metal lines in a process of manufacturing the second metal lines. A method for manufacturing the display panel and a display device are also provided.

Abstract: Array substrate, display panel and display device are provided. The array substrate includes multiple scanning lines, multiple data lines, multiple shift registers and multiple switching units. Each shift register is used for inputting a scanning signal to one terminal of a corresponding scanning line, the other terminal of each scanning line is connected with a first terminal of the switching unit, a second terminal of the switching unit receives a first reference voltage, a control terminal of the switching unit receives a first control signal. The shift register and the switching unit simultaneously pull down a voltage level of the scanning line to a low level. The present invention can realize a narrow frame, increase the user experience and ensure that the time that the voltage level of the scanning line pulled to the low level is the same.

Abstract: The present disclosure provides a liquid crystal display device including a plurality of pixels arranged in an array, each of the pixels comprising: a first pixel region and a second pixel region aligned vertically with the first pixel region. Any two adjacent pixels in the same row have structures being mirror-symmetric with respect to each other. And, for any two adjacent rows of pixels, a structure of the mth pixel in the (N+1)th row and a structure of the (m+1)th pixel in the Nth row are the same, where N and M are natural numbers.

Abstract: Disclosed are a GOA circuit and a liquid crystal display device. The GOA circuit includes multistage GOA sub-circuits. Each stage of GOA sub-circuit includes a pull-up control unit, a pull-up unit, a transfer unit, a pull-down unit, a pull-down holding unit and a bootstrap unit. The bootstrap unit includes a first capacitor, a second capacitor, a first thin-film transistor and a second thin-film transistor. The first capacitor and the second capacitor are used as coupling capacitors for node Q so as to boost a voltage at node Q and enhance driving capability of the GOA circuit.

Abstract: Disclosed are a GOA circuit and a liquid crystal display device. The GOA circuit includes multiple stages of GOA sub-circuits connected in cascade. In a pull-down unit of a GOA sub-circuit, a first thin film transistor and a second thin film transistor are connected in series. Leakage current at Q point in the GOA circuit can be reduced, stability of the GOA circuit can be improved in harsh environments, and reliability of a liquid crystal panel can be enhanced.

Abstract: Disclosed are a GOA circuit and a liquid crystal display device. The GOA circuit includes multistage GOA sub-circuits. Each stage of GOA sub-circuit includes a pull-up control unit, a pull-up unit, a transfer unit, a pull-down unit, a pull-down holding unit and a bootstrap unit. The bootstrap unit includes a first capacitor, a second capacitor, a first thin-film transistor and a second thin-film transistor. The first capacitor and the second capacitor are used as coupling capacitors for node Q so as to boost a voltage at node Q and enhance driving capability of the GOA circuit.

Abstract: An array substrate includes a carrier plate, a first heat dissipation layer, and a function layer sequentially stacked on each other. The function layer is arranged on one side facing a user. The function layer includes a plurality of drive devices, metal wires and connection sections arranged between the plurality of drive devices. The plurality of drive devices are formed with openings. The connection sections each have an end extending through the openings to connect with one of the drive devices and an opposite end extending across the metal wires to connect with an adjacent one of the drive devices. The first heat dissipation layer conducts heat from the metal wires, the plurality of drive devices, and the connection sections through the carrier plate for dissipation. A method for manufacturing the array substrate and a display device are also provided.

Abstract: Disclosed are a liquid crystal display panel and a gate driving circuit thereof. The liquid crystal display panel includes a plurality of pixel units arranged in a matrix, a plurality of scan lines, a gate driving circuit, a plurality of data lines and a data driving circuit. Every two scan lines are corresponded to the pixel units in the same column and alternatively connected to the pixel units in the same column. Each data line is connected to the pixel units in the two rows. The driving abilities of the gate driving signals provided to the two scan lines corresponding to the pixel units in the same column are different. In this manner, the liquid crystal display panel can have less brightness variation and thus have a better display performance.