Abstract: The concepts and technologies disclosed herein are directed to proximity routing policy enforcement for trans-border Internet of Things (“IoT”) data governance compliance. A network gateway can receive, from a data source device, a device registration message comprising a device registration header. The network gateway can determine, based upon the device registration header and a data governance policy, whether the data source device is permitted to access a data governance zone. In response to determining that the data source device is permitted to access the data governance zone, the network gateway can determine, based upon a further data governance policy, at least one gateway of a plurality of gateways operating in the data governance zone to which the device registration message is to be forwarded. The network gateway can forward the registration message to the at least one gateway so that the at least one gateway is enabled for device operation.

Abstract: Inverting tube apparatuses having an inverting tube (e.g., a knitted tube) that is configured to roll into an inversion support catheter and capture material from within a body lumen such as a blood vessel, in which the knitted tube is configured to prevent locking down onto the outside of the inversion support catheter. The inversion support catheter may include an expandable funnel at the distal end thereof having an interior profile that is adapted to capture and break apart hard material captured by the tractor so that it may be pulled into the inversion support catheter for removal.

Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

Abstract: Techniques are disclosed relating to multi-block fetches for cache misses. In some embodiments, cache tag circuitry maintains a tag value that is shared by multiple cache blocks. In response to a miss, the cache may initiate a fetch request to a next level cache or memory. Aggregation circuitry may aggregate multiple fetch requests for cache blocks that share the tag value and fetch circuitry may initiate a single multi-block fetch operation to the next level cache or memory that returns cache blocks for the aggregated multiple fetch requests. In various embodiments, disclosed techniques may improve performance (e.g., by reducing fetch bus transactions), reduce power consumption, or both, relative to traditional techniques.

Abstract: Systems and methods according to present principles provide for three axis force sensing in a convenient and manufacturable way. In one implementation, a vibrating motor is attached at the fixed end of an anisotropic structure, such as a rod, which then vibrates in a circular motion. A monitor such as a 3-axis accelerometer is also attached to the anisotropic structure. The resulting motion is then mapped electronically for analysis. With no force applied, a circular motion is achieved. When a net force is applied to the free, vibrating end of the rod, the circular pattern which is traced out becomes distorted, e.g., progressively flattened into an ellipse, in a repeatable way which is directly proportional to the applied force. The axis of the applied force can be ascertained according to the direction in which the ellipse forms. Systems and methods according to present principles may be used in any application in which force sensing is needed, e.g., robotics, including robotic surgery.

Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a well region in a substrate and forming an anti-punch through region in a top portion of the well region. The method further includes forming a barrier layer over the anti-punch through region and alternately stacking first semiconductor material layers and second semiconductor material layers over the barrier layer. The method further includes patterning the first semiconductor material layers, the second semiconductor material layers, the barrier layer, and the anti-punch through region to form a fin and removing the first semiconductor material layers and the barrier layer to expose the anti-punch through region. The method further includes forming a gate wrapping around the second semiconductor material layers.

Abstract: Example embodiments described herein therefore relate to an object-model based event detection system that comprises a plurality of sensor devices, to perform operations that include: generating sensor data at the plurality of sensor devices; accessing the sensor data generated by the plurality of sensor devices; detecting an event, or precursor to an event, based on the sensor data, wherein the detected event corresponds to an event category; accessing an object model associated with the event type in response to detecting the event, wherein the object model defines a procedure to be applied by the event detection system to the sensor data; and streaming at least a portion of a plurality of data streams generated by the plurality of sensor devices to a server system based on the procedure, wherein the server system may perform further analysis or visualization based on the portion of the plurality of data streams.

Abstract: A system and method for creating a dynamic electronic form are described. The system may include one or more processors that cause the system to perform create an electronic form with one or more data entry fields. The system may also obtain access to a plurality of datasets, where each dataset may include multiple entry fields and integrate at least one identified dataset with the electronic form. The system may further suggest at least one data input in the data entry field based on information input in the data entry field by a user. The data entry input suggested may be sourced from the identified dataset integrated to the electronic form.

Abstract: A method for reducing stress induced defects in heterogeneous epitaxial interfaces of a semiconductor device is disclosed. The method includes forming a fin structure with a fin base, a superlattice structure on the fin base, forming a polysilicon gate structure on the fin structure, forming a source/drain (S/D) opening within a portion of the fin structure uncovered by the polysilicon gate structure, modifying the first surfaces of the first layers to curve a profile of the first surfaces, depositing first, second, and third passivation layers on the first, second, and third surfaces, respectively, forming an epitaxial S/D region within the S/D opening, and replacing the polysilicon gate structure with a metal gate structure. The superlattice structure includes first and second layers with first and second lattice constants, respectively, and the first and second lattice constants are different from each other.

Abstract: Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, a memory system implements a storage hierarchy that includes first cache circuitry and second cache circuitry at different levels of the hierarchy. Processor circuitry generates write data to be written to the memory system. In some embodiments, first compression circuitry is configured to compress a first block of write data in response to full accumulation of the first block in the first cache circuitry and second compression circuitry is configured to compress a second block of write data in response to full accumulation of the second block in the second cache circuitry. Write circuitry may write the first and second compressed blocks of data in a single combined write to a higher level in the storage hierarchy.

Abstract: A data center rack system includes a rack housing that includes side panels and a top panel coupled to the side panels, the top and side panels defining a rack volume sized to enclose a plurality of data center server rack trays, each of the data center server rack trays configured to support a plurality of heat generating electronic devices; and a rack bottom coupled to the side panels to at least partially define the rack volume, the rack bottom including a bottom panel having a top surface coupled to the side panels and a plurality of blocks coupled to a bottom surface of the bottom panel opposite the top surface, at least one pair of the plurality of blocks defining an opening between the blocks and below the bottom surface of the bottom panel and sized to receive a lifting member of a lifting machine.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over the substrate. The semiconductor device further includes a first channel layer and a second channel layer and a first insulating structure interposing the first channel layer and the semiconductor layer and a second insulating structure interposing the first channel layer and the second channel layer. The semiconductor device further includes a gate stack abutting the first channel layer and the second channel layer, and the gate stack includes a first portion vertically sandwiched between the first channel layer and the semiconductor layer and a second portion vertically sandwiched between the first channel layer and the second channel layer.

Abstract: Techniques are disclosed relating to caching for address translation. In some embodiments, address translation circuitry is configured to process requests to translate addresses in a first address space to addresses in a second address space. The translation circuitry may include cache circuitry configured to store translation information, arbitration circuitry configured to arbitrate among ready requests for access to entries of the cache, and hazard circuitry. The hazard circuitry may assign a first request to an ready status the arbitration circuitry based on detection of an absence of hazards for a first address of the first request and add a second request to a queue of requests for the arbitration circuitry based on detection of a hazard for a second address of the second request. Independent arbitration for requests without hazards may improve performance in various aspects, relative to traditional techniques.

Abstract: The concepts and technologies disclosed herein are directed to time-aware blockchain staged regulatory control of Internet of Things (“IoT”) data. A federation platform can receive a registration request from an enterprise edge platform to register a blockchain identifier for publication of public data on a public blockchain. The federation platform can determine if the registration request contains any restricted data parameters. In response to determining that the registration request does not contain any restricted data parameters, the federation platform can query a security module to obtain an encryption key. The federation platform can receive the encryption key from the security module. The federation platform can store the encryption key in association with the blockchain identifier and an enterprise edge platform ID that uniquely identifies the enterprise edge platform.

Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

Abstract: Methods and apparatus for classifying and/or discriminating particles in an aerosol. An example method involves delivering a flow of the aerosol through a nozzle into a sampling volume and directing a plurality of light beams onto an interaction plane in the sampling volume. The plurality of light beams may each be made up of light having one of a corresponding plurality of different wavelengths. For example, the wavelengths may include wavelengths of visible and infrared light or visible, near infrared and short wave infrared light. The method may detect intensities of light from the plurality of light beams that has been scattered at the interaction plane by particles of the aerosol at a plurality of different scattering angles. The resulting data is processed to characterize and/or discriminate the particles.