Abstract: Disclosed is a solar cell, including: a substrate; an emitter, a first passivation film, an antireflection film and a first electrode sequentially disposed on an upper surface of the substrate; a tunneling layer, a retardation layer, a field passivation layer, a second passivation film and a second electrode sequentially disposed on a lower surface of the substrate. The retardation layer is configured to retard a migration of a doped ion in the field passivation layer to the substrate. The retardation layer includes a first retardation sub-layer overlapping with a projection of the second electrode and a second retardation sub-layer misaligning with a projection of the second electrode, and at least the second retardation sub-layer is an intrinsic semiconductor. A thickness of the first retardation sub-layer is smaller than a thickness of the second retardation sub-layer in a direction perpendicular to the surface of the substrate.

Abstract: A stacked multijunction solar cell having a dielectric insulating layer system, a germanium substrate, which forms an underside of the multijunction solar cell, a germanium subcell and at least two III-V subcells, which follow each other in the specified order, the insulating layer system includes a layer sequence made up of at least one bottom insulating layer, which is integrally connected to a first surface section of the multijunction solar cell and a top insulating layer forming an upper side of the insulating layer system, and a metal coating of the multijunction solar cell is integrally and electrically conductively connected to a second surface section abutting the first surface section of the multijunction solar cell and is integrally connected to a section of the upper side of the insulating layer system, and the top insulating layer comprises amorphous silicon or is made up of amorphous silicon.

Abstract: VCSELs designed to emit light at a characteristic wavelength in a wavelength range of 910-2000 nm and formed on a silicon substrate are provided. Integrated VCSEL systems are also provided that include one or more VCSELs formed on a silicon substrate and one or more electrical, optical, and/or electro-optical components formed and/or mounted onto the silicon substrate. In an integrated VCSEL system, at least one of the one or more electrical, optical, and/or electro-optical components formed and/or mounted onto the silicon substrate is electrically or optically coupled to at least one of the one or more VSCELs on the silicon substrate. Methods for fabricating VCSELs on a silicon substrate and/or fabricating an integrated VCSEL system are also provided.

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. An epitaxial pillar of SiGe or Ge extends upward from the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric layer is arranged over an upper surface of the substrate and is disposed around the lower epitaxial region to extend over outer edges of the well region. The dielectric layer has inner sidewalls that contact outer sidewalls of the epitaxial pillar. A dielectric sidewall structure has a bottom surface that rests on an upper surface of the dielectric layer and has inner sidewalls that extend continuously from the upper surface of the dielectric layer to a top surface of the epitaxial pillar.

Abstract: Provided is an image pickup device, including: a first trench provided between a plurality of pixels in a light-receiving region of a semiconductor substrate, the semiconductor substrate including the light-receiving region and a peripheral region, the light-receiving region being provided with the plurality of pixels each including a photoelectric conversion section; and a second trench provided in the peripheral region of the semiconductor substrate, wherein the semiconductor substrate has a variation in thickness between a portion where the first trench is provided and a portion where the second trench is provided.

Abstract: A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.

Abstract: Diffusion-based and ion implantation-based methods are provided for fabricating planar photodetectors. The methods may be used to fabricate planar photodetectors comprising type II superlattice absorber layers but without mesa structures. The fabricated planar photodetectors exhibit high quantum efficiencies, low dark current densities, and high specific detectivities as compared to photodetectors having mesa structures.

Abstract: Micro light-emitting diode (LED) displays, and fabrication and assembly of micro LED displays, are described. In an example, a pixel element for a micro-light emitting diode (LED) display panel includes a blue color nanowire or nanopyramid LED above a first nucleation layer above a substrate, the blue color nanowire or nanopyramid LED including a first GaN core. A green color nanowire or nanopyramid LED is above a second nucleation layer above the substrate, the green color nanowire or nanopyramid LED including a second GaN core. A red color nanowire or nanopyramid LED is above a third nucleation layer above the substrate, the red color nanowire or nanopyramid LED including a GaInP core.

Abstract: A device may include: a highly doped n+ Si region; an intrinsic silicon multiplication region disposed on at least a portion of the n+ Si region, the intrinsic silicon multiplication having a thickness of about 90-110 nm; a highly doped p? Si charge region disposed on at least part of the intrinsic silicon multiplication region, the p? Si charge region having a thickness of about 40-60 nm; and a p+ Ge absorption region disposed on at least a portion of the p? Si charge region; wherein the p+ Ge absorption region is doped across its entire thickness. The thickness of the n+ Si region may be about 100 nm and the thickness of the p? Si charge region may be about 50 nm. The p+ Ge absorption region may confine the electric field to the multiplication region and the charge region to achieve a temperature stability of 4.2 mV/°C.

Abstract: A light detecting device includes a light absorbing layer configured to absorb light in a wavelength range from visible light to short-wave infrared (SWIR); a first semiconductor layer provided on a first surface of the light absorbing layer; an anti-reflective layer provided on the first semiconductor layer and comprising a material having etch selectivity with respect to the first semiconductor layer; and a second semiconductor layer provided on a second surface of the light absorbing layer. The first semiconductor layer has a thickness less than 500 nm so as to be configured to allow light to transmit therethrough in the wavelength range from visible light to SWIR.

Abstract: An integrated circuit system, structure and/or component is provided that includes an integrated electrical power source in a form of a unique, environmentally-friendly energy harvesting element or component. The energy harvesting component provides a mechanism for generating autonomous renewable energy, or a renewable energy supplement, in the integrated circuit system, structure and/or component. The energy harvesting element includes a first conductor layer, a low work function layer, a dielectric layer, and a second conductor layer that are particularly configured to promote electron migration from the low work function layer, through the dielectric layer, to the facing surface of the second conductor layer in a manner that develops an electric potential between the first conductor layer and the second conductor layer. An energy harvesting component includes a plurality of energy harvesting elements electrically connected to one another to increase a power output of the electric harvesting component.

Abstract: A semiconductor device including: a semiconductor substrate having a first and a second side, and including a donor layer with a doping concentration profile in a depth direction from the first to the second side. The donor layer includes: a first peak, situated at a first distance from the first side of said substrate; a first region adjacent to the first peak and extending in the depth direction from the first peak toward the first side, a second peak in said doping concentration profile, situated at a second distance from the first side of said substrate. Said second distance is less than said first distance and greater than zero; and a second region adjacent to the second peak and extending in the depth direction from the second peak toward the first side of the substrate, which has a doping concentration which is substantially uniform.

Abstract: A positive-intrinsic-negative (PIN) photosensitive device is provided. A p-type semiconductor layer composed of molybdenum oxide and having valence band energy between valence band energy of an intrinsic semiconductor layer and an upper electrode is used to replace a p-type semiconductor layer used in a conventional PIN photodiode, so that the PIN photodiode may be prepared without using borane gas. More, a difference between valence band energy of the p-type semiconductor layer and the intrinsic semiconductor layer is used to transport holes located in a valence band, so that it is unnecessary to use an active layer of a thin film transistor, so that the PIN photosensitive device may be stacked on the thin film transistor to reduce aperture ratio loss of a display panel.

Abstract: The method comprises fabricating a plurality of sub-units on a planar substrate, where each sub-unit comprises an optical sensing structure configured to receive at least a portion of an optical wavefront that impinges on one or more of the sub-units, and material forming at least a portion of a hinge in a vicinity of a border with at least one adjacent sub-unit; removing at least a portion of the substrate on respective borders between each of at least three different pairs of sub-units to enable relative movement between the sub-units in each pair constrained by one of the hinges formed from the material; and providing one or more actuators configured to apply a force to fold a connected network of multiple sub-units into a non-planar formation.

Abstract: An electro-optical device includes a substrate, a pixel electrode disposed at the substrate, and a pixel circuit portion disposed between the substrate and the pixel electrode. The pixel circuit portion includes a scanning line disposed along a first direction, a data line disposed along a second direction intersecting the first direction, a first constant potential line disposed along the scanning line, a second constant potential line disposed along the data line, and a transistor disposed corresponding to an intersection position of the scanning line and the data line and including a gate electrode electrically coupled to the scanning line, a source region electrically coupled to the data line, and a drain region electrically coupled to the pixel electrode. The pixel circuit portion also includes a coupling portion disposed corresponding to the intersection position and configured to electrically couple the first constant potential line and the second constant potential line.

Abstract: Structures for a photodetector and methods of fabricating a structure for a photodetector. The structure includes a light-absorbing region having a side edge, an anode adjacent to the side edge of the light-absorbing region, and a cathode adjacent to the side edge of the light-absorbing region.

Abstract: An optoelectronic semiconductor component and a method for producing an optoelectronic semiconductor component are disclosed.

Abstract: A switch is provided for a communication device operating in the RF or microwave frequency range. The switch can include one or more PIN diodes and a biasing circuit that includes one or more inductors. When operating at RF and/or microwave frequencies, the switch can be configured as a low pass filter using the parasitic inductances and capacitances of the PIN diodes and inductors to minimize the insertion loss of the switch. The parasitic capacitances for the low pass filter can be provided by operating the inductors of the switch above their self-resonant frequency such that the inductors operate like capacitors. The parasitic inductances for the low pass filter can be provided by the PIN diodes.

Abstract: The present disclosure relates to a method of forming a semiconductor device structure. The method may be performed by forming a gate structure along a first side of a semiconductor substrate. The semiconductor substrate is thinned. Thinning the semiconductor substrate causes defects to form along a second side of the semiconductor substrate opposing the first side of the semiconductor substrate. Dopants are implanted into the second side of the semiconductor substrate after thinning the semiconductor substrate. The semiconductor substrate is annealed to form a doped layer after implanting the dopants. The doped layer is formed along the second side of the semiconductor substrate.

Abstract: According to an embodiment of the present disclosure, a photodetector device can include a substrate layer; a bottom contacting layer disposed over a surface of the substrate layer and having a first contacting region and a second contacting region, the bottom contacting layer providing a low resistance path between the first and second contacting regions; an insulating layer disposed over a surface of the bottom contacting layer; an intrinsic region disposed within the insulating layer, the intrinsic region in electrical contact with the first contacting region of the bottom contacting layer, the intrinsic region comprising a low band-gap material; a metal contact disposed within the insulating layer and in electrical contact with the second contacting region of the bottom contacting layer; an anode in electrical contact with the intrinsic region; and a cathode in electrical contact with the metal contact.

Abstract: To Provide a back contact type solar cell with high photovoltaic-conversion efficiency which can be easily manufactured with good yield at low cost. The high photovoltaic-conversion efficiency solar cell of the present invention includes on a back surface, as a non-light receiving surface, of a first conductive type semiconductor substrate: a first conductive type diffusion layer where first conductive type impurities are diffused; a second conductive type diffusion layer where second conductive type impurities are diffused; and a high resistive layer or an intrinsic semiconductor layer formed between the first conductive type diffusion layer and the second conductive type diffusion layer.

Abstract: An organic light emitting display device includes a light emitting layer for emitting light and for displaying an image, a fingerprint sensor for detecting a fingerprint, and a circuit element layer disposed between the light emitting layer and the fingerprint sensor and configured to control the light emitting layer. The fingerprint sensor includes a light receiver. The light receiver overlaps the light emitting layer and has an uneven surface.

Abstract: An optoelectronic device having a textured layer is described. In an aspect, a method may be used to produce the optoelectronic device, where the method includes epitaxially growing a semiconductor layer of the optoelectronic device on a growth substrate, and exposing the semiconductor layer to an etching process to create at least one textured surface in the semiconductor layer. The textured semiconductor layer can be referred to as a textured layer. The etching process is performed without the use of a template layer, or similar layer, configured as a mask to generate the texturing. The etching process can be done by one or more of a liquid or solution-based chemical etchant, gas etching, laser etching, plasma etching, or ion etching. The method can also include lifting the semiconductor layer of the optoelectronic device from the growth substrate by, for example, the use of an epitaxial lift off (ELO) process.

Abstract: The photodiode device comprises a substrate (1) of semiconductor material with a main surface (10), a plurality of doped wells (3) of a first type of conductivity, which are spaced apart at the main surface (10), and a guard ring (7) comprising a doped region of a second type of conductivity, which is opposite to the first type of conductivity. The guard ring (7) surrounds an area of the main surface (10) including the plurality of doped wells (3) without dividing this area. Conductor tracks (4) are electrically connected with the doped wells (3), which are thus interconnected, and further conductor tracks (5) are electrically connected with a region of the second type of conductivity. A doped surface region (2) of the second type of conductivity is present at the main surface (10) and covers the entire area between the guard ring (7) and the doped wells (3).

Abstract: A carrier layout comprising a substrate comprising a ground plane layer and a coplanar waveguide interconnect disposed onto the substrate. The coplanar waveguide interconnect comprises a pair of coplanar conductors and a central conductor disposed between the pair of coplanar conductors. The coplanar conductors of the pair are electrically connected to each other by at least one conducting island that is isolated from the ground plane layer. The present invention also provides an interconnect structure for coupling an electronic unit to an optical device disposed on a substrate having a ground plane layer, the interconnect structure comprising a pair of coplanar conductors and a central conductor disposed between the pair of coplanar conductors. The conductors of the pair are electrically connected by at least one conducting island that is isolated from the ground plane layer.

Abstract: An electrically-powered device, structure and/or component is provided that includes an attached electrical power source in a form of a unique, environmentally-friendly energy harvesting element or component. The energy harvesting component provides a mechanism for generating autonomous renewable energy, or a renewable energy supplement, in the integrated circuit system, structure and/or component. The energy harvesting element includes a first conductor layer, a low work function layer, a dielectric layer, and a second conductor layer that are particularly configured in a manner to promote electron migration from the low work function layer, through the dielectric layer, to the facing surface of the second conductor layer in a manner that develops an electric potential between the first conductor layer and the second conductor layer. The energy harvesting component includes a plurality of energy harvesting elements electrically connected to one another to increase an electrical power output.

Abstract: A unique, environmentally-friendly energy harvesting element is provided for generating autonomous renewable energy, or a renewable energy supplement, in electronic systems, electronic devices and electronic system components. The energy harvesting element includes a first conductor layer, a low work function layer, a dielectric layer, and a second conductor layer that are particularly configured in a manner to promote electron migration from the low work function layer, through the dielectric layer, to the facing surface of the second conductor layer in a manner that develops an electric potential between the first conductor layer and the second conductor layer. Electric leads are provided to connect the energy harvesting element to a load to power the load with the energy harvesting element. An energy harvesting component is also provided that includes a plurality of energy harvesting elements electrically connected to one another to increase a power output of the electric harvesting component.

Abstract: A diode is provided, the diode including: a semiconductor layer of a first conductivity type, configured to have a trench structure and be an epitaxial layer of a wide gap semiconductor; a semiconductor layer of a second conductivity type, configured to be at least in contact with a side wall of the trench structure and be an epitaxial layer of the wide gap semiconductor; and an electrode configured to be in contact with the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type, on the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type.

Abstract: A method for fabricating a contact hole of an array substrate, an array substrate and a display device are disclosed, the method includes: coating a topmost layer with a first photoresist coating, exposing but not developing a part of the first photoresist coating, corresponding to a first contact hole, in an exposure process; coating the first photoresist coating with a second photoresist coating, exposing a part of the second photoresist coating, corresponding to the first contact hole, in an exposure process; developing and removing exposed parts of the first and second photoresist coatings, wherein a size of a removed part of the second photoresist coating, corresponding to the first contact hole, is smaller than a size of a removed part of the first photoresist coating, corresponding to the first contact hole; and removing parts of functional film layers, corresponding to the first contact hole, to form the first contact hole.

Abstract: A photodiode has an absorption layer and a cap layer operatively connected to the absorption layer. A pixel is formed in the cap layer and extends into the absorption layer to receive charge generated from photons therefrom. The pixel defines an annular diffused area to reduce dark current and capacitance. A photodetector includes the photodiode. The photodiode includes an array of pixels formed in the cap layer. At least one of the pixels extends into the absorption layer to receive charge generated from photons therefrom. At least one of the pixels defines an annular diffused area to reduce dark current and capacitance.

Abstract: A component for detecting UV radiation and a method for producing a component are disclosed. In an embodiment a component includes a semiconductor body including a first semiconductor layer, a second semiconductor layer and an intermediate active layer located therebetween, wherein the semiconductor body is based on AlmGa1-n-mInnN with 0?n?1, 0?m?1 and n+m<1, wherein the first semiconductor layer is n-doped, wherein the second semiconductor layer is p-doped, wherein the active layer is formed with respect to its material composition in such a way that during operation of the component, arriving ultraviolet radiation is absorbed by the active layer for generating charge carrier pairs, wherein the active layer is relaxed with respect to its lattice constant, and wherein the first semiconductor layer is strained with respect to its lattice constant.

Abstract: The present application discloses an electro-static discharge (ESD) transistor array apparatus, and relates to the field of semiconductor technologies.

Abstract: An optical waveguide integrated light receiving element includes an optical waveguide (105) arranged on a side of a second contact layer (102) opposite to a side where a light absorption layer (103) is arranged, having a waveguide direction parallel to a plane of the light absorption layer (103), and optically coupled with the second contact layer (102). The second contact layer (102) has, in a planar view, a size of an area smaller than that of the light absorption layer (103) and arranged inside the light absorption layer (103).

Abstract: The disclosure relates to an epitaxial structure. The epitaxial structure includes a substrate, an epitaxial layer, and a nanotube film. The substrate has an epitaxial growth surface. The epitaxial layer is located on the epitaxial growth surface of the substrate. The nanotube film is located between the substrate and the epitaxial layer. The nanotube film includes a number of nanotubes orderly arranged and combined with each other by ionic bonds.

Abstract: A dye-sensitized solar cell formed by layering a conductive layer; a photoelectric conversion layer in which a dye is adsorbed in a porous semiconductor layer and the layer is filled with a carrier transporting material; and a counter electrode including only a counter electrode conductive layer or including a catalyst layer and a counter electrode conductive layer on a support made of a light transmitting material, in which the photoelectric conversion layer is brought into contact with the counter electrode; the porous semiconductor layer forming the photoelectric conversion layer has two or more layers with different light scattering properties; and the two or more porous semiconductor layers are layered in an order of from a layer with lower light scattering property to a layer with higher light scattering property from a light receiving face side of the dye-sensitized solar cell.

Abstract: A semiconductor device comprises a layer sequence formed by a plurality of polar single crystalline semiconductor material layers that each has a crystal axis pointing in a direction of crystalline polarity and a stacking direction of the layer sequence. A core layer sequence is formed by an active region made of an active layer stack or a plurality of repetitions of the active layer stack. The active layer stack has an active layer having a first material composition associated with a first band gap energy, and carrier-confinement layers embedding the active layer on at least two opposite sides thereof, having a second material composition associated with a second band gap energy larger than the first band gap energy. A pair of polarization guard layers is arranged adjacent to the active region and embedding the active region on opposite sides thereof.

Abstract: A method of manufacturing a CIGS-based solar cell including a transparent rear electrode, the method comprising forming a rear electrode layer including a transparent oxide material; forming rear electrode patterns including a metal material on the rear electrode layer; forming a CIGS-based light absorption layer on the rear electrode layer on which the rear electrode patterns are formed; forming a buffer layer on the light absorption layer; and forming a front electrode including a transparent material on the buffer layer, wherein the rear electrode patterns are provided with a transmissive portion, through which light is transmitted, formed between patterns of the metal material.

Abstract: A semiconductor device comprises a layer sequence formed by a plurality of polar single crystalline semiconductor material layers that each have a crystal axis pointing in a direction of crystalline polarity and a stacking direction of the layer sequence. A core layer sequence is formed by an active region made of an active layer stack or a plurality of repetitions of the active layer stack. The active layer stack has an active layer having a first material composition associated with a first band gap energy, and carrier-confinement layers embedding the active layer on at least two opposite sides thereof, having a second material composition associated with a second band gap energy larger than the first band gap energy. A pair of polarization guard layers is arranged adjacent to the active region and embedding the active region on opposite sides thereof. Both polarization guard layers have the first material composition.

Abstract: Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering.

Abstract: A vertical positive-intrinsic-negative (pin) diode includes a semiconductor substrate in which a P-type region, an intrinsic region, and an N-type region are sequentially disposed in a vertical direction to be formed therein, a first electrode formed on one surface of the semiconductor substrate to be in electrical contact with the P-type region, and a second electrode formed on the other surface of the semiconductor substrate to be in electrical contact with the N-type region, wherein the P-type region and the N-type region are respectively disposed in an upper portion and a lower portion of the semiconductor substrate to be opposite to each other.

Abstract: Photodetector including: a waveguide of a waveguide material extending over a substrate; an insulating layer formed over the waveguide and having an opening exposing the waveguide; a photodetector layer formed over the insulating layer and into the opening so as to make contact with the waveguide, the photodetector layer having a first end at the opening and a second end distal from the opening, the photodetector layer being a gradient material of the waveguide material and germanium wherein a waveguide material portion of the gradient material varies from a maximum at the first end to a minimum at the second end and wherein a germanium portion of the gradient material varies from a minimum at the first end to a maximum at the second end; a photodetector region at the second end; and a photodetector layer extension extending at an angle from the photodetector layer at the second end.

Abstract: An image sensor array is disclosed. The image sensor array includes: a semiconductor substrate; a lateral photo detector structure over the semiconductor substrate, wherein the lateral photo detector structure has a dislocation trapping region protruding to the semiconductor substrate; and an insulating layer disposed over the lateral photo detector structure and further extending to a space between the lateral photo detector structure and the semiconductor substrate; wherein the lateral photo detector structure includes a first type region and a second type region having a polarity opposite to a polarity of the first type region, and the first type region extends at least along a portion of a boundary between an upside of the intrinsic region and the insulating layer. An associated manufacturing method is also disclosed.

Abstract: Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.

Abstract: A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.

Abstract: Diode barrier infrared detector devices and superlattice barrier structures are disclosed. In one embodiment, a diode barrier infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, and a barrier layer adjacent to the absorber layer, and a second contact layer adjacent to the barrier layer. The barrier layer includes a diode structure formed by a p-n junction formed within the barrier layer. The barrier layer may be such that there is substantially no barrier to minority carrier holes. In another embodiment, a diode barrier infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, a barrier layer adjacent to the absorber layer, and a diode structure adjacent to the barrier layer. The diode structure includes a second contact layer.

Abstract: A semiconductor device includes a middle field stop layer having a first conductivity type impurity concentration higher than a drift layer and arranged at a position in the drift layer. A ratio of a depth of the position of the middle field stop layer from a front surface of a semiconductor substrate to a thickness of the semiconductor substrate is equal to or greater than fifteen percent and equal to or less than thirty-five percent. When an IGBT is arranged in the semiconductor device, vibration of a collector voltage waveform in a switching off of the IGBT is restricted. When a diode is arranged in the semiconductor device, vibration of a recovery waveform in a recovery operation of the diode is restricted. Accordingly, at least one of the vibrations of the recovery waveform and the collector voltage waveform in the switching is restricted.

Abstract: An image pickup apparatus includes a first pixel electrode connected to a pixel circuit, a second pixel electrode adjoining the first pixel electrode and connected to the pixel circuit, a photoelectric conversion film continuously covering the first and second pixel electrodes, and an opposite electrode facing the first and second pixel electrodes via the film. The film includes a recessed portion recessed toward a portion between the first and second pixel electrodes on a surface opposite to the first and second pixel electrodes. The depth of the recessed portion is greater than the first pixel electrode's thickness, and a distance from the first pixel electrode to the recessed portion is greater than a distance from the first pixel electrode to the second pixel electrode. The opposite electrode is provided continuously along the surface via the film, and the recessed portion surrounds a part of the opposite electrode.

Abstract: A semiconductor device includes a substrate, a first insulation layer formed on the substrate in a first region, a photon absorption seed layer formed on the first insulation layer in the first region and on the substrate in a second region separate from the first region, and a photon absorption layer formed on the photon absorption seed layer in the first region. The photon absorption seed layer has a particular structure that may assist in reducing dislocation density in a region that includes a photon absorption layer.

Abstract: Tunneling field effect transistors and fabrication methods thereof are provided, which include: obtaining a gate structure disposed over a substrate structure; and providing a source region and a drain region within the substrate structure separated by a channel region, the channel region underlying, at least partially, the gate structure, and the providing including: modifying the source region to attain a narrowed source region bandgap; and modifying the drain region to attain a narrowed drain region bandgap, the narrowed source region bandgap and the narrowed drain region bandgap facilitating quantum tunneling of charge carriers from the source region or the drain region to the channel region. Devices including digital modulation circuits with one or more tunneling field effect transistor(s) are also provided.

Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes an element region and a termination region provided around the element region. The termination region has a first semiconductor region of a first conductivity type provided at the first surface of the semiconductor substrate and a second semiconductor region of a second conductivity type provided between the first semiconductor region and the second surface. The semiconductor device further includes a first insulating film provided on the first semiconductor region, a second insulating film provided on the first semiconductor region and having a portion interposed between the first insulating films, a first electrode provided on the first surface of the element region and electrically connected to the first semiconductor region, and a second electrode provided at the second surface of the semiconductor substrate.