Abstract: Certain example embodiments of this invention relate to photovoltaic modules that include high contact angle coatings on one or more outermost major surfaces thereof, and/or associated methods. In certain example embodiments, the high contact angle coatings advantageously reduce the likelihood of electrical losses through parasitic leakage of the electrical current caused by moisture on surfaces of the photovoltaic modules, thereby potentially improving the efficiency of the photovoltaic devices. In certain example embodiments, the high contact angle coatings may be nitrides and/or oxides of or including Si, Ti, Ta, TaCr, NiCr, and/or Cr; hydrophobic DLC; and/or polymer-based coatings. The photovoltaic modules may be substrate-type modules or superstrate-type modules in different example embodiments.

Abstract: A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.

Abstract: An image sensor device includes a substrate including a light sensing region therein and a reflective structure on a first surface of the substrate over the light sensing region. An interconnection structure having a lower reflectivity than the reflective structure is provided on the first surface of the substrate adjacent to the reflective structure. A microlens is provided on a second surface of the substrate opposite the first surface. The microlens is configured to direct incident light to the light sensing region, and the reflective structure is configured to reflect portions of the incident light that pass through the light sensing region back toward the light sensing region. Related devices and fabrication methods are also discussed.

Abstract: Methods for forming a resistive transparent buffer layer on a substrate are provided. The method can include depositing a resistive transparent buffer layer on a transparent conductive oxide layer on a substrate. The resistive transparent buffer layer can comprise a cadmium doped tin oxide that has an as-deposited stoichiometry where cadmium is present in an atomic amount that is less than 33% of a total atomic amount of tin and cadmium. Zinc may also be provided in the resistive transparent buffer layer in certain embodiments. Additionally, thin film photovoltaic devices having such resistive transparent buffer layers are provided.

Abstract: A method of manufacturing a crystalline silicon solar cell, subsequently including: providing a crystalline silicon substrate having a first side and a second side opposite the first side; pre-diffusing Phosphorus into a first side of the substrate to render a Phosphorus diffused layer having an initial depth; blocking the first side of the substrate; exposing a second side of the substrate to a Boron diffusion source; heating the substrate for a certain period of time and to a certain temperature so as to diffuse Boron into the second side of the substrate and to simultaneously diffuse the Phosphorus further into the substrate.

Abstract: A solar cell including a first conductive type semiconductor substrate; a first conductive type first semiconductor layer on a back surface of the semiconductor substrate; a second conductive type second semiconductor layer on the back surface of the semiconductor substrate at a height different from the first semiconductor layer, the second semiconductor layer being separated from the first semiconductor layer; and a passivation layer on the back surface of the semiconductor substrate. The passivation layer covers at least a portion of the first semiconductor layer and at least a portion of the second semiconductor layer. The passivation layer includes impurities.

Abstract: Multi-crystalline silicon processing techniques are provided. In one aspect, a method for roughening a multi-crystalline silicon surface is provided. The method includes the following steps. The multi-crystalline silicon surface is coated with a diblock copolymer. The diblock copolymer is annealed to form nanopores therein. The multi-crystalline silicon surface is etched through the nanopores in the diblock copolymer to roughen the multi-crystalline silicon surface. The diblock copolymer is removed. A multi-crystalline silicon substrate with a roughened surface having a plurality of peaks and troughs is also provided, wherein a distance from one peak to an adjacent peak on the roughened surface is from about 20 nm to about 400 nm.

Abstract: Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.

Abstract: A structure and method of manufacture is disclosed for a backside thinned imager that incorporates a conformal, Al2O3, low thermal budget, surface passivation. This passivation approach facilitates fabrication of backside thinned, backside illuminated, silicon image sensors with thick silicon absorber layer patterned with vertical trenches that are formed by etching the exposed back surface of a backside-thinned image sensor to control photo-carrier diffusion and optical crosstalk. A method of manufacture employing conformal, Al2O3, surface passivation approach is shown to provide high quantum efficiency and low dark current while meeting the thermal budget constraints of a finished standard foundry-produced CMOS imager.

Abstract: A semiconductor light detection device fabrication technique is provided in which the cap etch and anti-reflection coating steps are performed in a single, self-aligned lithography module.

Abstract: This disclosure provides systems, methods, and apparatus related to semiconductor photomultipliers. In one aspect, a device includes a p-type semiconductor substrate, the p-type semiconductor substrate having a first side and a second side, the first side of the p-type semiconductor substrate defining a recess, and the second side of the p-type semiconductor substrate being doped with n-type ions. A conductive material is disposed in the recess. A p-type epitaxial layer is disposed on the second side of the p-type semiconductor substrate. The p-type epitaxial layer includes a first region proximate the p-type semiconductor substrate, the first region being implanted with p-type ions at a higher doping level than the p-type epitaxial layer, and a second region disposed on the first region, the second region being doped with p-type ions at a higher doping level than the first region.

Abstract: A nano-scale tower structure array having increased surface area on each tower for gathering incident light is provided for use in three-dimensional solar cells. Embodiments enhance surface roughness of each tower structure to increase the surface area available for light gathering. Enhanced roughness can be provided by manipulating passivation layer etching parameters used during a formation process of the nano-scale tower structures, in order to affect surface roughness of a photoresist layer used for the etch. Manipulable etching parameters can include power, gas pressure, and etching compound chemistry.

Abstract: Methods and apparatus for forming solar cells with selective emitters are provided. A method includes positioning a substrate on a substrate receiving surface. The substrate has a surface comprising a first patterned heavily doped region having a first dopant concentration that defines the selective emitters, and a second doped emitter region having a second dopant concentration that is less than the first dopant concentration, wherein the second doped emitter region surrounds the first patterned heavily doped region. The method further comprises determining a position of the first patterned heavily doped region by using a Fourier transform to process a filtered optical image, aligning one or more distinctive elements in a screen printing mask with the first patterned heavily doped region by using information received from the determined position of the first patterned heavily doped region, and depositing a layer of material on a portion of the first patterned heavily doped region.

Abstract: A multi-junction III-V photovoltaic device is provided that includes at least one top cell comprised of at least one III-V compound semiconductor material; and a bottom cell in contact with a surface of the at least one top cell. The bottom cell includes a germanium-containing layer in contact with the at least one top cell, at least one intrinsic hydrogenated silicon-containing layer in contact with a surface of the germanium-containing layer, and at least one doped hydrogenated silicon-containing layer in contact with a surface of the at least one intrinsic hydrogenated silicon-containing layer. The intrinsic and doped silicon-containing layers can be amorphous, nano/micro-crystalline, poly-crystalline or single-crystalline.

Abstract: Embodiments of a process comprising forming a pixel on a front side of a substrate, thinning the substrate, depositing a doped silicon layer on a backside of the thinned substrate, and diffusing a dopant from the doped silicon layer into the substrate. Embodiments of an apparatus comprising a pixel formed on a front side of a thinned substrate, a doped silicon layer formed on a backside of the thinned substrate, and a region in the thinned substrate, and near the backside, where a dopant has diffused from the doped silicon layer into the thinned substrate. Other embodiments are disclosed and claimed.

Abstract: A photovoltaic device, such as a solar cell, having improved performance is provided. The photovoltaic device includes a copper-containing layer that contains an amount of impurities therein which is sufficient to hinder the diffusion of copper into an underlying semiconductor substrate. The copper-containing layer, which is located within a grid pattern formed on a front side surface of a semiconductor substrate, includes an electroplated copper-containing material having an impurity level of 200 ppm or greater located atop at least one metal diffusion barrier layer.

Abstract: A photovoltaic device, such as a solar cell, having improved performance is provided. In one embodiment, the photovoltaic device includes a multimetal semiconductor alloy layer located on exposed portions of a front side surface of a semiconductor substrate. The multimetal semiconductor alloy layer includes at least a first elemental metal that forms an alloy with a semiconductor material, and a second elemental metal that differs from the first elemental metal and that does not form an alloy with a semiconductor material at the same temperature as the first elemental metal. The photovoltaic device further includes a copper-containing layer located atop the multimetal semiconductor alloy layer.

Abstract: A method for processing solar cells comprising: providing a vertical furnace to receive an array of mutually spaced circular semiconductor wafers for integrated circuit processing; composing a process chamber loading configuration for solar cell substrates, wherein a size of the solar cell substrates that extends along a first surface to be processed is smaller than a corresponding size of the circular semiconductor wafers, such that multiple arrays of mutually spaced solar cell substrates can be accommodated in the process chamber, loading the solar cell substrates into the process chamber; subjecting the solar cell substrates to a process in the process chamber.

Abstract: Provided are a photomultiplier and a manufacturing method thereof. The manufacturing method thereof may include forming a mask layer on an active region of a substrate doped with a first conductive type, ion implanting a second conductive type impurity opposite to the first conductive type into the substrate to form a first doped region in the active region under the mask layer and an non-active region exposed from the mask layer, forming a device isolation layer on the non-active region, removing the mask layer, and ion implanting the second conductive type impurity having a concentration higher than that of the first doped region into an upper portion of the first doped region in the active region to form a second doped region shallower than the first doped region.

Abstract: An optoelectronic device including at least one of a solar device, a semiconductor device, and an electronic device. The device includes a semiconductor unit. A plurality of metal fingers is disposed on a surface of the semiconductor unit for electrical conduction. Each of the metal fingers includes a pad area for forming an electrical contact. The optoelectronic device includes a plurality of pad areas that is available for connection to a bus bar, wherein each of the metal fingers is connected to a corresponding pad area for forming an electrical contact.

Abstract: In a solid state imaging device, and a method of manufacture thereof, the efficiency of the transfer of available photons to the photo-receiving elements is increased beyond that which is currently available. Enhanced anti-reflection layer configurations, and methods of manufacture thereof, are provided that allow for such increased efficiency. They are applicable to contemporary imaging devices, such as charge-coupled devices (CCDs) and CMOS image sensors (CISs). In one embodiment, a photosensitive device is formed in a semiconductor substrate. The photosensitive device includes a photosensitive region. An anti-reflection layer comprising silicon oxynitride is formed on the photosensitive region. The silicon oxynitride layer is heat treated to increase a refractive index of the silicon oxynitride layer, and to thereby decrease reflectivity of incident light at the junction of the photosensitive region.

Abstract: To provide a method for manufacturing a solar cell, whereby solar cells can be mass-produced by a simple process at low cost. A first conductivity-type silicon powder (11) is prepared, a silicon powder layer (11a) is formed by disposing the powder in the form of a layer, the powder layer is melted by heating the powder layer to the melting point of silicon or higher, and a first conductivity-type silicon layer (11b) is formed by cooling the melted layer. A second conductivity-type silicon powder (12) is prepared, a second conductivity-type silicon powder layer (12a) is formed by disposing the powder in the form of a layer on the first conductivity-type silicon layer (11b), the powder layer is melted by heating the powder layer to the melting point of silicon or higher, and a second conductivity-type silicon layer (12b) is formed by cooling the melted layer.

Abstract: A device for depositing a layer containing at least two components on an object, including: a deposition chamber; a source containing a material to be deposited; and a control device, which controls the deposition process, implemented such that a concentration of the component of the material can be modified in its gas phase prior to deposition on the object by selective binding a specified quantity of the component, wherein the selectively bound quantity of the component is controlled by modifying a control parameter that is actively coupled to a binding rate or the component, and wherein the control device contains a gettering element containing a reactive material containing copper and/or molybdenum. Also, a method for depositing a layer containing at least two components on an object, wherein a selectively bound quantity of a component is controlled by modifying a binding rate of the component of the control device.

Abstract: An image sensing device includes a light-shielding film having transit portions, a first film and a second film. The second film comprises a first layer having a different refractive index from the first film. The first layer lies within at least the transit portions, and forms interfaces with the first film. The distance between the interface and the corresponding photoelectric conversion portion is greater than the distance between the photoelectric conversion portion and the lower end of the corresponding transit portion.

Abstract: A CMOS image sensor is disclosed. The CMOS imager includes a lightly doped semiconductor substrate of a first conductivity type. At least one CMOS pixel of a second conductivity type is formed in the semiconductor substrate. The semiconductor substrate is configured to receive a bias voltage applied for substantially depleting the semiconductor substrate and for forming a depletion edge within the semiconductor substrate. A well of the second conductivity type substantially surrounds the at least one CMOS pixel to form a depletion region about the at least one CMOS pixel operable to form a minimum predetermined barrier to the depletion edge within the semiconductor substrate to pinch off substrate bias in proximity to the return contact.

Abstract: The photovoltaic cell includes an electrically conductive passivation film separated from an electrically conductive collection layer and a substrate. An electrically conductive connection pattern maintains an area of the collection layer in suspension with respect to the passivation film. Suspension of the collection layer is obtained by making an etching agent pass through a permeable area of the collection layer.

Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a first light shielding layer disposed on the second surface of the substrate; and a second light shielding layer disposed on the first light shielding layer and directly contacting with the first light shielding layer, wherein a contact interface is between the first light shielding layer and the second light shielding layer.

Abstract: A photovoltaic device is provided that includes a semiconductor substrate including a p-n junction with a p-type semiconductor portion and an n-type semiconductor portion one on top of the other. A plurality of patterned antireflective coating layers is located on a p-type semiconductor surface of the semiconductor substrate, wherein at least one portion of the p-type semiconductor surface of the semiconductor substrate is exposed. Aluminum is located directly on the at least one portion of the p-type semiconductor surface of the semiconductor substrate that is exposed.

Abstract: Described herein is a novel material that easily penetrates silicon nitride-based anti-reflective coatings, forming a high quality electrical contact. A method for metallization on a solar cell includes depositing a passivation layer on a silicon substrate of a solar cell, depositing derivatized metal particles onto the passive layer, heating the substrate of the solar cell to migrate surface coatings from the derivatized metal particles onto the passivation layer creating a diffusion Channel through passivation layer to the silicon substrate, and as the metal particles melt due to the heating on the substrate, the melted metal diffuses through the diffusion channel forming a metallic content with the silicon substrate.

Abstract: Provided are a photoelectric conversion device capable of controlling an absorbance of the red region at a wavelength of 600 nm or more, and an imaging device having an improved color reproduction by using the photoelectric device. Provided are a photoelectric conversion device that includes a pair of electrodes, and a photoelectric conversion layer disposed between the pair of electrodes, in which the photoelectric conversion layer contains a p-type semiconductor compound and two or more different kinds of unsubstituted fullerenes, and an imaging device that includes the photoelectric conversion device.

Abstract: A solar cell includes a base and a nanostructured layer formed on the base. The nanostructured layer has a nanostructured surface opposite the base. The nanostructured surface has a quasi-periodic, anisotropic array of elongated ridge elements having a wave-ordered structure pattern, each ridge element having a wavelike cross-section and oriented substantially in a first direction.

Abstract: Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described.

Abstract: An image sensor includes a light receiving device, a field effect transistor, a stress layer pattern, and a surface passivation material. The light receiving device is formed in a first region of a substrate. The field effect transistor is formed in a second region of the substrate. The stress layer pattern is formed over the field effect transistor for creating stress therein to improve transistor performance. The surface passivation material is formed on the first region of the substrate for passivating dangling bonds at the surface of the light receiving device.

Abstract: Processes for fabricating photovoltaic devices in which the front side contact metal semiconductor alloy metallization patterns have a uniform thickness at edge portions as well as a central portion of each metallization pattern are provided.

Abstract: Ultra-high reflectivity is projected for internal reflectors comprised of a metal film and nanostructured transparent conductive oxide (TCO) bi-layer on the back side of a semiconductor device. Oblique-angle deposition can be used to fabricate indium tin oxide (ITO) and other TCO optical thin-film coatings with a porous, columnar nanostructure. The resulting low-n dielectric films can then be employed as part of a conductive omni-directional reflector (ODR) structure capable of achieving high internal reflectivity over a broad spectrum of wavelengths and a wide range of angles. In addition, the dimensions and geometry of the nanostructured, low-n TCO films can be adjusted to enable diffuse reflections via Mie scattering. Diffuse ODR structures enhance the performance of light trapping and light guiding structures in photonic devices.

Abstract: A solar cell and a method for manufacturing the same are discussed. The solar cell includes a substrate of a first conductive type, an emitter region of a second conductive type opposite the first conductive type, the emitter region forming a p-n junction along with the substrate, a passivation layer which is positioned on a back surface of the substrate and has a plurality of via holes exposing portions of the back surface of the substrate, a first electrode connected to the emitter region, and a second electrode which is positioned on a back surface of the passivation layer and is connected to the substrate through the plurality of via holes.

Abstract: A method for integrating a slotted waveguide into a CMOS process is disclosed. A slot can be patterned on a SOI wafer by etching a first pad hard mask deposited over the wafer. The slot is then filled with a plug material by depositing a second pad hard mask over the first pad hard mask. A waveguide in association with one or more electronic and photonic devices can also be patterned on the SOI wafer. The trenches can be filled with an isolation material and then polished. Thereafter, the first and second pad hard masks can be stripped from the wafer. The slot can once again be filled with the plug material and patterned. After forming one or more electronic and photonic devices on the wafer using the standard CMOS process, a via can be opened up down to the nitride plug and the nitride plug can then be removed.

Abstract: The invention provides a material for forming a passivation film for a semiconductor substrate. The material includes a polymer compound having an anionic group or a cationic group.

Abstract: A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.

Abstract: The present invention provides methods for forming a buffer layer for Group IBIIIAVIA solar cells. The buffer layer is formed using chemical bath deposition and the layer is formed in steps. A first buffer layer is formed on the absorber and the first buffer layer is then treated using etching, oxidizing, annealing or some combination thereof. Subsequently a second buffer layer is then positioned on the treated surface. Additional buffer layers can be added following treatment of the previously deposited layer.

Abstract: A method for generating electric power including the steps of: (a) preparing a solar cell having a condensing lens and a solar cell element, wherein the solar cell element includes an n-type GaAs layer, a p-type GaAs layer, a quantum tunneling layer, an n-type InGaP layer, a p-type InGaP layer, a p-type window layer, an n-side electrode, and a p-side electrode, and satisfies the following equation (I): d2<d1, d3<d1, 1 nanometer?d2?4 nanometers, 1 nanometer?d3?4 nanometers, d5<d4, d6<d4, 1 nanometer?d5?5 nanometers, 1 nanometer?d6?5 nanometers, 100 nanometers?w2, 100 nanometers?w3, 100 nanometers?w4, and 100 nanometers?w5 . . . (I); and (b) irradiating a region S which is included in the surface of the p-type window layer through the condensing lens with light to satisfy the following equation (II) in order to generate a potential difference between the n-side electrode and the p-side electrode: w6?w1 . . . (II).

Abstract: A solar cell module is manufactured by resin-sealing a solar cell having a surface electrode to which a tab wire is connected, a tab wire is connected to the surface electrode and the solar cell is sealed with a sealing resin at a relative low temperature during the resin sealing step. For such purposes, a thin-film solar cell having a surface electrode to which a tab wire is connected is resin-sealed with a conductive adhesive film by using a decompression laminator, whereby the thin-film solar cell module is manufactured. A decompression laminator having a first chamber and a second chamber partitioned by a flexible sheet is used. Each chamber is capable of independent internal pressure adjustment. The second chamber includes a heating stage capable of heating. A resin mutually compatible with the thermoplastic resin constituting the conductive adhesive film is used as the sealing resin.

Abstract: An array of series-connected solar cells is formed on a support layer with at least a two cells being adjacent and a third solar cell being either adjacent or separated from the second solar cell. A portion of the photovoltaic junction layer is separated from the first solar cell. The semiconducting material of the first type of the separated portion is electrically connected with the semiconducting material of the second type of the second solar cell through physical contact between the front electrode of the first cell and the back electrode of the second cell. The material of the second type of the separated portion of the junction layer is connected with the semiconducting material of the first type of the third cell to define a bypass diode that is in parallel and in opposition to the second and the third solar cells.

Abstract: The instant disclosure relates to contact grids for use in photovoltaic cells, wherein a cross-section of the contact grid fingers is shaped as a trapezoid, as well as a method of making photovoltaic cells comprising these contact grids. The contact grids of the instant disclosure are cost effective and, due to their thick metal grids, exhibit minimum resistance. Despite having thick metal grids, the unique shape of the contact grid fingers of the instant disclosure allow the photovoltaic cells in which they are employed to retain more solar energy than traditional solar cells by reflecting incoming solar energy back onto the surface of the solar cell instead of reflecting this energy away from the cell.

Abstract: A method of manufacturing a solar cell comprises the steps of: forming a lower conductor layer on a front side of a substrate; firing the lower conductor layer at a first temperature to form a first portion embedded into a doped region of the substrate and a second portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the lower conductor layer such that the second portion is disposed in the ARC layer; forming an upper conductor layer, corresponding to the lower conductor layer and electrically connected to the lower conductor layer, on the ARC layer; and firing the upper conductor layer at a second temperature to form a first portion embedded into the ARC layer and a second portion, which is exposed out of the ARC layer.

Abstract: A solar cell module and a method for manufacturing the same are discussed. The method for manufacturing a solar cell module includes forming a front protective member including a hardened first silicone resin on a first surface of a front substrate; disposing a plurality of solar cells on the front protective member; forming a back protective member including a hardened second silicone resin and a fiber material on the plurality of solar cells; and disposing a back substrate on the fiber material.

Abstract: A CMOS image sensor, in which an implantation process is performed on substrate under isolation structures each disposed between two adjacent photosensor cell structures. The implantation process is a destructive implantation to form lattice effects/trap centers. No defect repair process is carried out after the implantation process is performed. The implants can reside at the isolation structures or in the substrate under the isolation structures. Dark leakage and crosstalk are thus suppressed.

Abstract: A photoelectric conversion device and a method of fabricating the same are disclosed. The photoelectric conversion device may include a first substrate having a first electrode and a first non-slip portion, a second substrate facing the first substrate and having a second electrode and a second non-slip portion and a sealing member. The photoelectric conversion device may further include an electrolyte solution positioned in a spaced formed between the first substrate, the second substrate, and the sealing member. The first substrate or the second substrate may be positioned to contact at least one of a first non-slip portion and a second non-slip portion.

Abstract: An integrated plasmonic sensing device is monolithically integrated and provides marker-free detection (eliminating the need to use fluorescent or absorbing markers) and in-situ monitoring of conditions at each detection region. The integrated plasmonic sensing device includes a plasmonic backplane disposed on a monolithically integrated image sensor. One or more plasmonic scattering regions and one or more plasmonic via regions laterally offset from the plasmonic scattering regions are provided in the plasmonic sensing device. Guided plasmonic modes mediate power transfer through the plasmonic backplane to one or more underlying image sensor pixels.

Abstract: Disclosed herein are a solar cell module and a method for manufacturing the same. According to an exemplary embodiment of the present invention, there is provided a solar cell module, including: a solar cell having electrode patterns formed on at least one surface thereof; and a parylene coating layer(s) forming a light transmissive passivation layer on at least a front surface of the solar cell. According to another exemplary embodiment of the present invention, there is provided a method for manufacturing a solar cell module, including: (a) preparing a solar cell having electrode patterns formed on at least one surface thereof; and (b) forming a light transmissive passivation layer by coating parylene on at least a front surface of the solar cell.