Abstract: An image sensor comprising a matrix of solid-state light sensor elements each representing a unit pixel, which is capable of reading out sensor signals from respective pixels in a time series by sequentially selecting pixels on a line-by-line basis and sequentially selecting pixels in a selected line, wherein each pixel line is divided into a plurality of blocks with each block composed of the same specified number of pixels and a first scanning means sequentially reads pixel sensor signals on the block-by-block basis starting from the first block and a second scanning means reads pixel sensor signals of the readout block. The image sensor thus constructed can achieve high speed scanning of respective pixels with a minimal increase in power consumption.

Abstract: A multi-cell cluster which includes a plurality of light-detecting unit cells and a single charge-integration and readout circuitry. Typically, each of the cells produces charge representative of the detected light. The circuit may be shared by the plurality of unit cells, and used to read-out the charge in real-time. The cluster may also include a switch associated with each unit cell, such that each switch connects its associated unit cell to the circuit. The switch may also be controlled in a time-multiplexing manner. Each unit cell may include a photodetector, a photodiode, or a photogate. The circuit may include a shared storage device, a shared reset circuit, or a readout circuit. Typically, the shared storage device may be for accumulating the charge in the focal plane. The here-above described apparatus facilitates either static or dynamic, either local or global image resolution/sensitivity tradeoffs.

Abstract: A pixel unit 1 comprises a nonvolatile memory transistor MT, which is formed on a p-type well 12 of a semiconductor substrate 10 and which has a floating gate 14 and a control gate 16, and selecting gate transistors ST1 and ST2 which share a diffusion layer 17 with the memory transistor MT and which is formed on both sides of the memory transistor MT. The memory transistor MT has a photoelectric converting region PD in the substrate directly below the floating gate 14. By irradiating the memory transistor MT with light while a positive writing voltage is applied to the control gate 16, charges generated in the photoelectric converting region PD are injected into the floating gate 14 to be held therein, so that pixel information is stored as a threshold voltage.

Abstract: Each of N optical detector parts 801 to 80N has a photodiode PD, a capacitor Cd and a switch SW0. An amplifier A1, an integrator circuit capacitor Cf1, and a switch SW11 , are connected in parallel between the input terminal and the output terminal of an integrator circuit 10. The capacitance of the integrator circuit capacitance C11 is equal to the capacitance of the capacitor Cd in each of the N optical detector parts 801 to 80N. A switch SW01, is equipped between the input terminal of the integrator circuit 10 and the switch SW0 for each of the N optical detector parts 801 to 80N. A switch SW02 is equipped between the output terminal of the integrator circuit 10 and the switch SW0 in each of the N optical detector parts 801, to 80N.

Abstract: In a photoelectric conversion device for reading signals in succession from plural photoelectric converting elements (S11-S33), arranged two-dimensionally on a substrate, by successively scanning drive lines (g1-g3) in the X-direction thereby transferring signals charges along signal lines in the Y-direction, for reading the signals of the photoelectric converting elements in a partial area, only the arbitrarily selected drive lines for the plural photoelectric converting elements are scanned in succession while the remaining drive lines are not driven or are driven simultaneously for transferring the charges at a timing different from the timing of drive of the arbitrarily selected drive lines.

Abstract: In a photoelectric conversion device having a plurality of pixel cells each of which includes a photoelectric conversion element, a field effect transistor having the gate area for storing signal charge generated by the photoelectric conversion element and the source-drain path for outputting a signal corresponding to the signal charge stored in the gate, a first power supply line for supplying electric power to the field effect transistor, and a first switch connected between the field effect transistor and the first power supply line, when a reset voltage for resetting the gate of the field effect transistor is Vsig0, a threshold voltage of the field effect transistor is Vth, current flowing through the field effect transistor is Ia, a voltage applied via the first power supply line is Vc1, and a series resistance of the first switch is Ron, each pixel cell is configured to satisfy a condition determined by Vc1−Ron×Ia>Vsig0−Vth.

Abstract: In a solid state image pickup device, in order to form a bypass region with precisely controlled impurity concentration and width, there is provided a solid state image pickup device comprising a photoelectric conversion unit composed of a first region of a first conductive type formed on a semiconductor substrate and having a principal surface, a second region of a second conductive type formed in the first region, and a third region of the first conductive type present between the second region and the principal surface, a fourth region of the second conductive type formed in the first region, and a charge transfer unit including the first region, an insulation layer on the first region and a control electrode provided on the insulation layer, for transferring a signal charge accumulated in the photoelectric conversion unit, to the fourth region, wherein the photoelectric conversion unit and the charge transfer unit are connected through a fifth region of the second conductive type.

Abstract: A physical quantity distribution sensor is disclosed. The sensor comprises: a plurality of sensor/storage sections each having a sensor element for sensing a received physical quantity and a storage element for storing the information of physical quantity sensed by the sensor element; a selector for selecting at least one of the sensor/storage sections; and a plurality of buffers each capable of detecting and supplying the information stored in at least one selected sensor/storage section. This sensor further comprises at least one selection signal transfer line for transferring an output of the selector. Power supply input portions of the buffers are connected to the selection signal transfer line, and the buffers are operated using, as a power voltage, an output of the selector entered into the buffers through the selection signal transfer line.

Abstract: An imaging system includes an array of pixel sensors and a mode control circuit. The array of pixel sensors is adapted to furnish logarithmically encoded indications of light intensities during a first mode and furnish linearly encoded indications of the light intensities during a second mode. The mode control circuit is adapted to selectively place the array in one of the first and second modes. The imaging system may include more than one array, and the mode control circuit may configure one of the arrays. The imaging system may include a camera, for example, that includes the array(s) and mode control circuit.

Abstract: In order to select an image pickup area and execute an image pickup operation, or to perform an interlace operation, or to vary an image pickup frequency for one image pickup sensor, there is provided an image pickup apparatus constructed by a 2-dimensional solid state image pickup sensor in which pixel data instructed by horizontal and vertical shift registers is accessed and read out and a timing generator to drive the 2-dimensional solid state image pickup sensor. With respect to horizontal and vertical shift pulses which are supplied from the timing generator and drive horizontal and vertical shift registers of the 2-dimensional solid state image pickup sensor, periods of the horizontal shift pulses and/or the vertical shift pulses are made variable.

Abstract: An image pickup apparatus including: a plurality of photoelectric conversion elements for photoelectrically converting light from an object, a first output line to which signals from the plurality of photoelectric conversion elements are successively outputted, a plurality of first switches connected to the first output line to output the signals from the plurality of photoelectric conversion elements to the first output line, a second output line to which a reference signal is supplied, a plurality of second switches connected to the second output line to supply the reference signal to the second output line, a scanning circuit which controls the plurality of first switches and the plurality of second switches, and a differential circuit which obtains a difference between the signal from the first output line and the signal from the second output line.

Abstract: Imaging system having a sensor array with photocells that permit the monitoring of light levels while the sensor is exposed to a scene, and the ability to accurately avoid saturation on a per column, row, or array basis. The sensor array supports variable dynamic range by allowing variable integration times for different columns or rows of the array, thereby improving image quality of a scene in which there are both strong and weak light areas. In one embodiment, the photocell includes a parasitic multi-emitter bipolar junction transistor (BJT) acting as a photodetector. The parasitic device is part of a saturation detection circuit and also supports an electronic shutter mechanism. The parasitic BJT also permits increased sensitivity over some previous CMOS approaches. The photocell design is also spatially efficient, using in one embodiment only four MOSFETs in addition to the parasitic BJT.

Abstract: Each unit pixel includes a photodiode, a reading selection transistor, a reading transistor, an amplifying transistor, a reset transistor, and a horizontal selection transistor, and thus a MOS image sensor of a dot-sequential reading 5-Tr type is formed. The reading selection transistor and the reading transistor are formed with a two-layer gate structure, and gate potential of the reading selection transistor and the reading transistor is set to a negative potential. Thereby, a lower layer of a gate region of the reading transistor and the reading selection transistor is controlled to a negative potential. Thus, depletion in the lower layer region is suppressed to reduce leakage current.

Abstract: A time-integrating pixel sensor having a photo-detector, a capacitor, a comparator and a pixel data buffer. In operation, the photo-current from the photo-detector charges the capacitor and produces a photo-voltage. The photo-voltage sensed by the capacitor and a reference voltage is compared with the comparator. If the photo-voltage exceeds the reference voltage, a global code value is latched into the pixel data buffer. The optical power falling on the photo-detector is determined from the latched code value. An array of sensors is incorporated into a semiconductor device together with circuitry to read and decode the pixel data buffers. The reference voltage may be varied in time to increase the dynamic range of the sensor.

Abstract: An electronic photosensitive apparatus, such as an image scanner in a digital copier, uses depleted-gate photosensors or photogates as the photosensitive elements therein. The linearity of the transfer circuit associated with each photogate or set of photogates is improved by placing a bias charge of predetermined magnitude on a phototransfer gate disposed downstream of the photogate prefatory to reading out an image signal from the photogate.

Abstract: In order to select an image pickup area and execute an image pickup operation, or to perform an interlace operation, or to vary an image pickup frequency for one image pickup sensor, there is provided an image pickup apparatus constructed by a 2-dimensional solid state image pickup sensor in which pixel data instructed by horizontal and veritical shift registers is accessed and read out and a timing generator to drive the 2-dimensional solid state image pickup sensor. With respect to horizontal and vertical shift pulses which are supplied from the timing generator and drive horizontal and vertical shift registers of the 2-dimensional solid state image pickup sensor, periods of the horizontal shift pulses and/or the vertical shift pulses are made variable.

Abstract: An imager pixel including a photodetector, a first MOS transistor functioning as the driver of a source follower amplifier during signal readout, a second MOS transistor serving as a pixel readout transistor, a third MOS transistor serving as a photodetector reset transistor, and a reset noise cancellation circuit including a fourth MOS transistor, first and second capacitances, and an amplifier having a gain which is the inverse of the ratio of the first to the second capacitance.

Abstract: Imaging system having a sensor array with photocells that permit the monitoring of light levels while the sensor is exposed to a scene, and the ability to accurately avoid saturation on a per column, row, or array basis. The sensor array supports variable dynamic range by allowing variable integration times for different columns or rows of the array, thereby improving image quality of a scene in which there are both strong and weak light areas. In one embodiment, the photocell includes a parasitic multi-emitter bipolar junction transistor (BJT) acting as a photodetector. The parasitic device is part of a saturation detection circuit and also supports an electronic shutter mechanism. The parasitic BJT also permits increased sensitivity over some previous CMOS approaches. The photocell design is also spatially efficient, using in one embodiment only four MOSFETs in addition to the parasitic BJT.

Abstract: The device for the acquisition and automatic processing of data obtained from optical codes comprises a CMOS optical sensor; an analog processing unit connected to the optical sensor; an analog/digital conversion unit connected to the analog processing unity; a logic control unit connected to the CMOS optical sensor, the analog processing unit and the analog/digital conversion unit; and a data-processing unit connected to the logic control unit and the analog/digital conversion unit. The CMOS optical sensor and at least one of the analog processing, analog/digital conversion, logic control and data processing units are integrated in a single chip. The data processing unit processes the digital signals corresponding to the image acquired by the CMOS sensor and extracts the optically coded data.

Abstract: An imaging array of photodiodes on a chip cut from a semiconductor wafer includes a guard diode at each cut edge to reduce leakage current from the cut edges when the imaging array is in use. The photodiodes and guard diode may be fabricated from the same materials during the same process step. Electrical contacts coupled to the imaging array provide a mechanism for applying a reverse electrical bias to the photodiodes and guard region with respect to the wafer.

Abstract: A memory and a switchable digital filter supply different numbers of digital distortion correction values. The supplied distortion correction values are converted to an analog distortion correction signal. A passive, analog low pass filter for the analog distortion correction signal generates an analog deflection signal. The low pass filter is optimized only for those of the analog deflection signals having a given sample rate. A controller varies the different numbers of the supplied distortion correction values to maintain the given sample rate of the analog deflection signal for different horizontal scanning rates. The controller selectively implements respective operating modes for different horizontal scanning frequencies in which no interpolated distortion correction values are supplied or different numbers of interpolated distortion correction values are supplied.

Abstract: In order to realize a photoelectric conversion apparatus capable of easily switching a mode requiring a wide dynamic range in obtaining a motion image and a mode requiring a reduction in noise in obtaining a still image, a mode switching means is used, when a refresh operation is performed for each photoelectric conversion element, to switch between a mode of setting the potential of one electrode of the photoelectric conversion element to be higher than the potential of the other electrode, and a mode of setting the potential of one electrode of the photoelectric conversion element to be lower than the potential of the other electrode, thereby arbitrarily changing the refresh voltage. With this operation, desired photoelectric conversion signals for a motion image and a still image can be obtained.

Abstract: In a photosensitive device wherein voltages are read sequentially from a dark, or dummy, photosensor and a plurality of active photosensors with each of a series of scans, a circuit downstream of the photosensors resets the offset value of the voltage signals, based on successive voltage readings from the dark photosensor. An RC averaging circuit maintains a running average of readings from the dark photosensor over a large number of scans. Signals from the dark photosensors are read a first time into the averaging circuit, and then signals from the dark photosensors are read directly to downstream video circuitry. This double readout of dark-photosensor signals enables precise calibration of both on-chip circuitry and downstream video circuitry.

Abstract: A correlated double sampling unit within a CMOS imager employs an image sensor having a plurality of photodetectors arranged in a series of rows and columns with a row addressing circuit, a column addressing circuit, a first sample and hold circuit allocated for each of the columns, a transfer circuit operatively connecting each of the columns to the first sample and hold circuit for each of the columns, and a plurality of second sample and hold circuits, each of the second sample and hold circuits being operatively connected to a subset of the first sample and hold circuits.

Abstract: A light receiving element is provided with a phototransistor and a light receiving MOS diode proximate thereto and having a gate electrode covering a portion of the base region of the phototransistor. The gate electrode permits transmission of a portion of received light. The light receiving MOS diode forms an inversion layer in a substrate adjacent the base of a phototransistor during the time photo charges are stored, and generated photo charges are stored in the inversion region and the base region of the phototransistor. During the storage state, the potential of the inversion region and the base region of the phototransistor is limited, so that the intensity of an electric field applied to an insulating film between the electrode and the semiconductor substrate is 0.7 MV/cm or less. Alternatively, the potential of the electrode in a waiting state is fixed or made floating, so that an electric field is not applied, and recombination at the surface of the semiconductor substrate is made stable.

Abstract: An MOS-type solid-state imaging apparatus includes unit cells arranged in a two-dimensional matrix, each unit cell being constituted by a photodiode, an amplification transistor having a gate to which an output from the photodiode is input, a vertical selection transistor connected in series with the amplification transistor, and a reset transistor connected between the drain and gate of the amplification transistor to discharge the signal from the photodiode, a plurality of vertical address lines connected to the gates of the vertical selection transistors and arranged in a row direction, a vertical address circuit for driving the vertical address lines, a plurality of vertical signal lines arranged in a column direction in which currents are read out from the amplification transistors, a plurality of load transistors each connected to one end of a corresponding one of the vertical signal lines, a plurality of horizontal selection transistors each connected to the other end of a corresponding one of the vert

Abstract: A solid state image pickup apparatus is constructed by arranging a plurality of photoelectric converting pixels each for accumulating charges produced by receiving a light energy and for amplifying the charges. Timings to start and finish the accumulation of the charges for each pixel in a photoelectric converting section are set to be equal to or slightly deviated from the accumulation timing. For this purpose, the apparatus has: a signal accumulating section in which signal accumulating cells having transistors are arranged; transfer sections 26, 29, and 31 each for transferring the signals of the photoelectric converting pixels as voltages to the control electrodes of the signal accumulating cells; and a reading circuit for outputting the signal from one of the main electrodes of the transistors of the signal accumulating cells.

Abstract: A photoelectric conversion device suitable for use as an element of a photodetector array includes a photodiode for generating a first signal charge in response to incident light, an output unit including a JFET, and at least one transistor having an electrode that generates a second signal charge in response to incident light. The first and second signal charges may be output separately or combined. The second signal charge, or the first and second signal charges combined, may be monitored during an exposure time to determine the desired end of the exposure. An image sensor array may have one or more pixels with such light monitoring capability. The output signal for monitoring the light may be output over a reset drain interconnection, directly from the monitoring pixel or through other pixels via inter-pixel MOSFETS. Exposure time may be controlled, by timing a shutter or a strobe or the like, based on the monitored accumulation of signal charge during exposure.

Abstract: An image sensor comprises switching elements 30 on a substrate 1. An insulating separation layer 9 is disposed over the switching elements so that a photodiode arrangement 20a disposed over the insulating separation layer 9, can overlap the switching elements 30 and occupy a maximum area of the image sensor. A barrier layer 10 is interposed between the insulating separation layer 9 and the photodiode arrangement 20a, which prevents degradation of the photodiode characteristics over time.

Abstract: A system and method is described for increasing effective integration time of an optical sensor including holding a first signal within each pixel cell, proportional to light integrated by the pixel cell over the previous frame period, generating a second signal within each pixel cell proportional to light integrated by the pixel cell over the current frame period, and summing the first signal and the second signal from each pixel, thereby producing an output signal representing the light integrated by each pixel over two frame periods.

Abstract: In the solid-state imaging apparatus of the present invention, when a signal is output from the capacity element to the data signal output circuit, the voltage of the output terminal of the capacity element is kept at that attained when the switch was previously opened, namely, the initial voltage of the input terminal of the data signal output circuit, whereby the voltage of the input terminal of the data signal output circuit is stable without fluctuation. Therefore, no noise is generated in the output signal at the instant when the capacity element and data signal output circuit are short-circuited, whereby optical images can be captured with a high accuracy in a high speed.

Abstract: A focal plane array comprising two-dimensionally arranged photodetectors, charge transfer devices, transfer gates and a pixel row selection circuit, the focal plane array being operated in such a manner that the signal charges are read out from the photodetectors to vertical charge transfer device in one horizontal retrace period and the signal charges stored in the vertical charge transfer device are transferred to outside of a photodetector array region, wherein the pixel row selection circuit comprises a shift register and a switching transistor connected between the shift register and the transfer gates; and by combination of driving the shift resister and driving the switching transistor the horizontal line is selected so that a photodetector from which signal charge is to be read out is selected.

Abstract: An amplifier type solid-state imaging device is operated in a capacitor load operation system. This solid-state imaging device is made high in reliability and an arrangement of the horizontal output circuit portion is simplified. The solid-state imaging device includes a plurality of pixel MOS transistors each of which is connected between a voltage source (V.sub.DD) and a vertical signal line, a control electrode thereof being connected to a scanning line and charges generated by photoelectric conversion being accumulated near the channel thereof, a load capacitor element connected between the vertical signal line and a first potential, and a reset MOS switch for resetting the load capacitor element to a reset potential. When a signal is read out, the potential of the load capacitor element is set to substantially the same potential as the channel potential of the pixel MOS transistor. The capacitance of the load capacitor element is set to be larger than the capacitance of the vertical signal line.

Abstract: A signal charge in an amplifying type solid-state imaging device of a capacitor load charge system can be detected efficiently. The amplifying type solid-state imaging device is composed of a plurality of pixel transistors, a load capacitor for accumulating signal charges of an amount corresponding to light incident on the pixel transistor, an operational amplifier having a first input terminal connected with the load capacitor element and a second input terminal to which a bias voltage is applied, a detection capacitor element connected in parallel to the operational amplifier and a reset switch (33) for resetting the detection capacitor element.

Abstract: In a photosensitive device wherein voltages are read sequentially from a dark, or dummy, photosensor and a plurality of active photosensors with each of a series of scans, a circuit downstream of the photosensors resets the offset value of the voltage signals, based on successive voltage readings from the dark photosensor. An RC circuit in parallel with the video line maintains a running average of readings from the dark photosensor over a large number of scans. This averaging of many dark-pixel readings averages out short-term thermal noise on the dark photosensor, for a truer offset value.

Abstract: A solid-state image pickup device includes a light receiving cell for accumulating electric charges created in response to a photo energy striking the gate of an amplification-type sensor and then produces a signal from the source region based on the accumulated carriers, a memory cell including an amplification-type memory cell having the same type as that of the abovementioned amplification-type sensor, to accumulate a signal transferred from the light receiving cell into the base region of the amplification-type memory cell, and a signal line for electrically connecting the source region of the light receiving cell and the source region of the memory cell. The shift of the accumulation start timing to each row of the light receiving cells is suppressed to a small value. The same signal can be read from the memory cell several times.

Abstract: A photosensor formed on an insulating substrate has a transparent top gate electrode arranged on the upper side of a semiconductor layer for photoelectric conversion and a bottom gate electrode arranged on the lower side of the semiconductor layer. If light is applied from the top gate electrode side in a state in which a bottom gate voltage V.sub.BG =+20 V is applied to the bottom gate electrode and a top gate voltage V.sub.TG =-20 V is applied to the top gate electrode, electron-hole pairs are generated in the semiconductor layer and only the holes are held in the semiconductor layer by the effect of the top gate voltage V.sub.TG =-20 V. Therefore, an n-channel is formed in the semiconductor layer and a drain current I.sub.DS flows. It was confirmed that the drain current I.sub.DS will not flow even if illumination light is applied when the bottom gate voltage V.sub.BG is set at 0 V. Therefore, the selection or non-selection state of the photosensor can be controlled by the bottom gate voltage V.sub.TG.

Abstract: An image array with improved dynamic range has at least one photosite, at least one column sense line and at least one column clamp transistor. A source of the photosite is coupled to the column sense line. A source of the column clamp transistor is coupled to the photosite source. A drain of the column clamp transistor is coupled to a drain of the photosite. A gate of the column clamp transistor is provided for application of a .phi..sub.cc signal. The .phi..sub.cc signal is coupled through a capacitance to the column sense line.

Abstract: A photosensor formed on an insulating substrate has a transparent top gate electrode arranged on the upper side of a semiconductor layer for photoelectric conversion and a bottom gate electrode arranged on the lower side of the semiconductor layer. If light is applied from the top gate electrode side in a state in which a bottom gate voltage V.sub.BG =+20 V is applied to the bottom gate electrode and a top gate voltage V.sub.TG =-20 V is applied to the top gate electrode, electron-hole pairs are generated in the semiconductor layer and only the holes are held in the semiconductor layer by the effect of the top gate voltage V.sub.TG =-20 V. Therefore, an n-channel is formed in the semiconductor layer and a drain current I.sub.DS flows. It was confirmed that the drain current I.sub.DS will not flow even if illumination light is applied when the bottom gate voltage V.sub.BG is set at 0 V. Therefore, the selection or non-selection state of the photosensor can be controlled by the bottom gate voltage V.sub.TG.

Abstract: A plurality of photosensors are formed on an insulation substrate in a matrix fashion. Each of the photosensors includes a photoelectric conversion semiconductor, first and second gate electrodes, a drain electrode and a source electrode. A signal line is connected to each drain electrode. After precharge signals are applied to the respective signal lines by driving a switching circuit, a sense voltage is applied to the first gate electrode, a selection voltage is applied to the second gate electrode, while a light beam is supplied to the photoelectric conversion semiconductor. As a result, the precharge voltages held on the signal lines are lowered by voltages corresponding to the intensity of the incident light beam.

Abstract: A general absolute value circuit for developing a true, symmetric or bipolar, absolute value output signal from an input charge signal, compact enough to be used on a sensor chip incorporated into (or used in combination with) a pixel processor of the type used in imaging and other systems that collect electromagnetic radiation as part of on-chip circuitry, includes a balanced differential amplifier combined with a merged dual shelf transistor structure. The balanced differential amplifier, in response to an input charge signal, drives the merged dual shelf transistor structure which in turn generates the desired true absolute value output signal. Such circuitry may be used in imaging systems to implement focal-plane processing algorithms or may be used for performing a single read true absolute value computation by a pixel processor located on a sensor chip. The merged dual shelf transistor structure enhances performance and speed of the processor in which it is incorporated.

Abstract: An imaging device includes an array of plural imaging elements each of which is responsive to incident light flux to provide an output signal. Each of the imaging elements includes provision for conducting a variable time integration of incident light flux, and alternatively, also for selecting a time interval during which each of the imaging elements simultaneously conducts such a time integration of incident light flux (i.e., takes a snap shot of an image scene). The imaging device includes provision for random access of each image element or group of image elements in the array so that output signals indicative of all or of only selected parts of an imaged scene can be processed for their image information, if desired.

Abstract: An image sensor can reduce fixed pattern noise (FPN) caused by transistors used for reading pixel signals. The image sensor comprises photodiodes D.sub.1, D.sub.2, . . . connected to a precharge line L.sub.PR through respective precharge transistors (Tr1).sub.1, (Tr1).sub.2 ; and pixel amplification transistors (Tr2).sub.1, (Tr2).sub.2, . . . , one end thereof being connected to a signal read line L.sub.RE, the other end thereof being grounded through respective pixel switching transistors (Tr3).sub.1, (Tr3).sub.2, . . . , and the gates thereof being connected to respective nodes between the precharge transistors Tr1, (Tr1).sub.2, . . . and the photodiodes D.sub.1, D.sub.2, . . . According to signals provided by a timing signal generator 3, the pixel switching transistors (Tr3).sub.1, (Tr3).sub.2, . . . are sequentially turned ON and OFF one after another.

Abstract: A photoelectric conversion device comprising a photoelectric conversion cell, as an individual pixel, comprises a first transistor having a control electrode region consisting of a semiconductor of one conduction type, and first and second main electrode regions consisting of a semiconductor of opposite conduction type of the one conduction type, for outputting a signal from the first main electrode region based on carriers transferred to the control electrode region, a carrier storage region provided adjacent the first transistor, consisting of a semiconductor of the one conduction type for storing carriers generated by light energy being received, and a second transistor, with the carrier storage region and the control electrode region of the transistor as the source and drain regions, for transferring carriers stored in the carrier storage region to the control electrode region of the transistor.

Abstract: The dynamic range of an image array photosite is improved by, first, turning on a column clamp transistor having a source coupled to a photosite transistor source and a drain coupled to a photosite transistor drain, wherein the column clamp transistor is turned on by a column clamp transistor gate voltage; then decreasing a current supplied to a column sense line below a quiescent value, wherein the column sense line is coupled to the photosite transistor source; then turning on the photosite transistor by a photosite transistor gate voltage; then turning off the photosite transistor and the column clamp transistor at substantially the same time; then increasing the current above the quiescent value; and then returning the current to the quiescent value.

Abstract: A photoelectric conversion device comprises a control circuit for applying a control signal to a control electrode of a photoelectric transducer, an operating point detection circuit for receiving an output signal from the photoelectric transducer and inverting an output state thereof depending on a level of the output signal, and a sample/hold circuit controlled by an output of the operating point detection circuit to hold a signal level corresponding to the control signal as developed when the output state of the operating point detection circuit is inverted, the signal held by the sample/hold circuit being read as a photoelectrically converted output. Photoelectric conversion characteristics thereby exhibits good linearity.

Abstract: An image reading device includes a plurality of photoelectric converting elements, a plurality of accumulating elements corresponding to each of the photoelectric converting elements, and switching circuitry for reading out the signals accumulated in the accumulating elements. Each of the photoelectric converting elements comprises a switching portion and a sensor portion. Driving circuitry is provided for driving the photoelectric converting elements by activating the switching portions to release the charges accumulated in the accumulating elements through the photoelectric converting elements in order to reset the accumulated elements.

Abstract: A solid-state imaging device comprises a semiconductor substrate, a plurality of pixels formed on the semiconductor substrate and generating imaging signals, and an output amplifier converting a pixel signal generated from the pixel to an imaging signal, and outputting the image signal. The pixel includes a photoelectric converting portion generating a charge in accordance with the amount of received light, a capacitor storing a charge generated from the photoelectric converting portion, and a switching portion for reading out the charge stored in the capacitor as the pixel signal. The capacitor includes a storing region formed on at least one of a part or an adjacent portion of the photoelectric converting portion, a capacitor insulating film formed on the storing region, the capacitor insulating film being made of a high dielectric material having a high relative dielectric constant, and a capacitor electrode formed on the capacitor insulating film.

Abstract: An improved contact image sensor (CIS) which uses a two-phase shift register is disclosed. The shift register is clocked by both phases of the clock signal, thereby doubling its speed. A transmission gate in the shift register is eliminated and combined with one of the inverters to allow two-phase operation and reduce the number of transistors required to implement the shift register.

Abstract: An active pixel sensor cell array in which a two-stage amplifier amplifies the output of each cell. The two-stage amplifier design reduces fixed pattern noise in the image data generated by reading the array, by providing increased gain for the output of each cell without impractically increasing the size and complexity of each cell. For each column of cells of the array, one part of the two-stage amplifier for each cell is shared by all cells of the column, and another part of the two-stage amplifier for each cell is included within the cell itself. Preferably, each cell includes only NMOS transistors (no cell includes a PMOS transistor). In preferred embodiments, a differential amplifier within each cell is the primary stage of the cell's output amplifier, PMOS load circuitry including a secondary output amplifier stage is shared by all cells of the column, and the two amplifier stages for each cell together comprise an op amp.