Abstract: A mechanism is provided for fabricating nanochannels for a nanodevice. Insulating film is deposited on a substrate. A nanowire is patterned on the film. Insulating material is deposited on the nanowire and film. A first circular hole is formed in the insulating material as an inlet, over a first tip of the nanowire to expose the first tip. A second circular hole is formed as an outlet, over a second tip of the nanowire opposite the first tip to expose the second tip. A nanochannel connects the first and second holes by etching away the nanowire via an etchant in the first and the second holes. A first reservoir is attached over the first hole in connection with the nanochannel at a previous location of the first tip. A second reservoir is attached over the second hole in connection with the nanochannel at a previous location of the second tip.

Abstract: A wavelength variable interference filter includes a fixed substrate, a movable substrate that faces the fixed substrate, a pair of reflective films, a fixed extraction electrode provided on the fixed substrate, and a movable connection electrode that is provided on the movable substrate and is in contact with the fixed extraction electrode at a connection position, in which the movable substrate includes a first groove that is provided at the connection position in a plan view in which the fixed substrate and the movable substrate are viewed from a substrate thickness direction, and a second groove that has a larger area than an area of the first groove in the plan view and is connected to the first groove.

Abstract: The invention relates to a method for manufacturing an apparatus for the processing of single molecules. According to this method, a self-assembling resist (155) is deposited on a processing layer (110, PL) and allowed to self-assemble into a pattern of two phases (155a, 155b). One of these phases (155a) is then selectively removed, and at least one aperture is generated in the processing layer (110, PL) through the mask of the remaining resist (155b). Thus apertures of small size can readily be produced that allow for the processing of single molecules (M), for example in DNA sequencing.

Abstract: A transparent conductive element easily formed by a printing method includes a substrate having a surface, and transparent conductive portions and transparent insulating portions that are alternately provided in a planar manner on the surface. Each of the transparent insulating portions is a transparent conductive layer including a plurality of hole elements provided two-dimensionally in a first direction and a second direction on the surface of the substrate. The hole elements that are adjacent in the first direction are connected to each other, and the hole elements that are adjacent in the second direction are connected to each other.

Abstract: Provided are a method of forming a through hole, which can inhibit misalignment between central axes of holes in both surfaces of a substrate, which is free from metal contamination, and which inhibits notching so as to improve the dimensional accuracy, the method including: preparing a silicon substrate; preparing a supporting substrate for supporting the silicon substrate; fixing the silicon substrate and the supporting substrate to form a composite substrate; and carrying out dry etching to the composite substrate from a silicon substrate side of the composite substrate toward a supporting substrate side of the composite substrate to form a through hole in the silicon substrate, in which the supporting substrate in the preparing a supporting substrate has a hole formed at a region corresponding to a region of the through hole to be formed in the silicon substrate, on a surface of the supporting substrate facing the silicon substrate.

Abstract: A lamellar structure graphite foil is used as a material for a separator for a fuel cell, and a hydrophobic layer is formed by impregnation on flow-field channels of the graphite foil. Such a separator is manufactured by forming the flow field channel by etching the graphite foil formed with the mask pattern thereon and forming a hydrophobic layer by impregnation. According to such a separator, performance of a fuel cell stack is enhanced and the manufacturing process of a separator is simplified.

Abstract: A nozzle plate manufacturing method that offers excellent protection against discharge liquid and that enables a nozzle plate having high nozzle-hole accuracy to be manufactured with good yield. The invention also provides a nozzle plate, a droplet discharge head manufacturing method, and a droplet discharge head.

Abstract: In some examples, a cooling system includes a silicon substrate defining a first trench, a second trench, and a plurality of channels extending between the first trench and the second trench. The silicon substrate may define a first surface and a second surface substantially opposite to and substantially parallel to the first surface, and each of the plurality of channels may extend substantially parallel to the surface of the silicon substrate. The cooling system also may include a microelectronic device comprising a heat-generating area. The microelectronic device may be attached to the first surface or the second surface of the silicon substrate. In some examples, the plurality of channels may be etched between the first trench and the second trench.

Abstract: The invention provides a transparent conducting film which comprises a compound of formula (I): Zn1-x[M]xO1-y[X]y(I) wherein: x is greater than 0 and less than or equal to 0.25; y is from 0 to 0.1; [X] is at least one dopant element which is a halgen; and [M] is: (a) a dopant element which is selected from: a group 14 element other than carbon; a lanthanide element which has an oxidation state of +4; and a transition metal which has an oxidation state of +4 and which is other than Ti or Zr; or (b) a combination of two or more different dopant elements, at least one of which is selected from: a group 14 element other than carbon; a lanthanide element which has an oxidation state of +4; and a transition metal which has an oxidation state of +4 and which is other than Ti or Zr. The invention further provides coatings comprising the films of the invention, processes for producing such films and coatings, and various uses of the films and coatings.

Abstract: A method for forming porous metal structures and the resulting structure may include forming a metal structure above a substrate. A masking layer may be formed above the metal structure, and then etched using a reactive ion etching process with a mask etchant and a metal etchant. Etching the masking layer may result in the formation of a plurality of pores in the metal structure. In some embodiments, the metal structure may include a first end region, a second end region, and an intermediate region. Before etching the masking layer, a protective layer may be formed above the first end region and the second end region, so that the plurality of pores is contained within the intermediate region. In some embodiments, the intermediate metal region may be a nanostructure such as a nanowire.

Abstract: To provide a reinforced electrolyte membrane to which breakage such as cracking is less likely to occur at the time of handling the reinforced electrolyte membrane during a period between after production of the reinforced electrolyte membrane and before conditioning operation of alkali chloride electrolysis, or at the time of disposing the reinforced electrolyte membrane in an electrolytic cell at the time of conditioning operation, and a process for producing the same. A reinforced electrolyte membrane 1 having an electrolyte membrane 10 containing a fluoropolymer having ion exchange groups, reinforced by a woven fabric 20 made of a reinforcing thread 22 and a sacrificial thread 24, wherein the sacrificial thread 24 remains in the electrolyte membrane 10, a void is formed between the sacrificial thread 24 and the electrolyte membrane 10, and 2000 ?m2<A<600 ?m2 and 0.3?B/A<1.

Abstract: Methods of reducing a registration error of a photomask are provided. A method of reducing a registration error of a photomask may include identifying the registration error with respect to a pattern element in a pattern region of the photomask. Moreover, the method may include reducing a thickness of a portion of a non-pattern region of the photomask by irradiating an energy beam onto a location of the non-pattern region of the photomask that is spaced apart from the pattern element, to generate stress at the pattern element. Related photomasks and methods of manufacturing an integrated circuit are also provided.

Abstract: The present disclosure is directed to a method of manufacturing a semiconductor structure in which a low-k dielectric layer is formed over a semiconductor substrate. Features can be formed proximate to the low-k dielectric layer by plasma etching with a plasma formed of a mixture of a CO2, CO, or carboxyl-containing source gas and a fluorine-containing source gas. The method allows for formation of damascene structures without encountering the problems associated with damage to a low-K dielectric layer.

Abstract: A method of forming an aperture (e.g., a through via, a blind via, a trench, an alignment feature, etc.) within a substrate includes irradiating a substrate with a laser beam to form a laser-machined feature having a sidewall. The laser-machined feature is then processed to change at least one characteristic (e.g., the sidewall surface roughness, diameter, taper, aspect ratio, cross-sectional profile, etc.) of the laser-machined feature. The laser-machined feature can be processed to form the aperture by performing an isotropic wet-etch process employing an etchant solution containing HNO3, HF and, optionally acetic acid.

Abstract: Optical stacks containing one or more patterned transparent conductor layers may be damaged by electrostatic discharges that occur during the optical stack manufacturing process. Such damage may result in non-conductive conductors within the patterned transparent conductor layer. An electrostatic discharge protected optical stack may include a substrate layer, a first anti-static layer having a sheet resistance of from about 106 ohms per square (?/sq) to about 109 ?/sq, and a patterned transparent conductor layer. Methods of testing and assessing damage to patterned transparent conductors are provided.

Abstract: An optical wiring substrate includes an insulation layer including a resin, and a conductor layer formed on the insulation layer and including a metal and an inclined surface inclined relative to an optical axis of an optical fiber. A first wiring pattern and a second wiring pattern are formed in the conductor layer, the first wiring pattern including a first connecting part to which a first electrode of a photoelectric conversion element is connected, and the second wiring pattern including a second connecting part to which a second electrode of the photoelectric conversion element is connected. A distance between the first wiring pattern and the second wiring pattern is narrowest between the first connecting part and the second connecting part. A distance between the first connecting part and the second connecting part is less than a dimension of the conductor layer in a thickness direction thereof.

Abstract: A traveling wave device includes a slow wave circuit supported by a dielectric membrane. The dielectric membrane can have a thickness substantially smaller than a wavelength of operation of the traveling wave device.

Abstract: A method of making a mold includes forming spaced mold cavities in a mold body. The mold cavities include geometrically similar portions, but have respective depths below an initial reference surface that vary as a function of position along a particular direction. The mold cavities can be formed using anisotropic etching of preferred crystal directions in single crystal materials such as silicon. A portion of the mold material adjacent the initial reference surface is removed to expose a new reference surface at a tilt angle with respect to the initial reference surface. The modified mold cavities have their respective axes at a new desired tilt angle relative to the new reference surface.

Abstract: A conductive glass substrate includes a glass substrate, a silicon dioxide layer, and a conductive mesh line, the glass substrate defines a meshed groove on a surface thereof; the silicon dioxide layer is attached to the surface of the glass substrate having the groove; the conductive mesh line have a shape adapted to that of the groove, the conductive mesh line is deposited in the groove and attached to the glass substrate via the silicon dioxide layer. In the conductive glass substrate, the conductive mesh line is received in the groove, compared with the conventional conductive glass substrate, a flexible substrate as a supporting body is not needed, the cost is down, and the structure of the conductive glass substrate is simple, further reducing the process, saving manpower and resources. A method of preparing the conductive glass substrate is provided.

Abstract: A wiring structure includes: an insulating film formed over a substrate; a plurality of wirings formed on the insulating film; and an inducing layer, which is formed on the insulating film in a region between the plurality of wirings, a constituent atoms of the wirings are diffused in the inducing layer.

Abstract: A mechanism is provided for forming a nanodevice. A reservoir is filled with a conductive fluid, and a membrane is formed to separate the reservoir in the nanodevice. The membrane includes an electrode layer having a tunneling junction formed therein. The membrane is formed to have a nanopore formed through one or more other layers of the membrane such that the nanopore is aligned with the tunneling junction of the electrode layer. The tunneling junction of the electrode layer is narrowed to a narrowed size by electroplating or electroless deposition. When a voltage is applied to the electrode layer, a tunneling current is generated by a base in the tunneling junction to be measured as a current signature for distinguishing the base. When an organic coating is formed on an inside surface of the tunneling junction, transient bonds are formed between the electrode layer and the base.

Abstract: A method of treating a wiring substrate according to an embodiment includes, in a semi-additive process: (1) contacting the wiring substrate with a pre-etching treatment liquid composition containing a chloride ion, the wiring substrate containing a seed layer formed of an electroless copper and a wiring pattern formed of an electrolytic copper; and (2) continuously, etching the wiring substrate with an etching liquid composition containing a hydrogen peroxide, a sulfuric acid, a tetrazole, a chloride ion, a copper ion and a water.

Abstract: A mechanism is provided for forming a nanodevice. A reservoir is filled with a conductive fluid, and a membrane is formed to separate the reservoir in the nanodevice. The membrane includes an electrode layer having a tunneling junction formed therein. The membrane is formed to have a nanopore formed through one or more other layers of the membrane such that the nanopore is aligned with the tunneling junction of the electrode layer. The tunneling junction of the electrode layer is narrowed to a narrowed size by electroplating or electroless deposition. When a voltage is applied to the electrode layer, a tunneling current is generated by a base in the tunneling junction to be measured as a current signature for distinguishing the base. When an organic coating is formed on an inside surface of the tunneling junction, transient bonds are formed between the electrode layer and the base.

Abstract: An implantable electrode array assembly configured to apply electrical stimulation to the spinal cord. A substantially electrically nonconductive layer of the device has a first portion positionable alongside the spinal cord that includes a plurality of first openings. The layer has a second portion that includes a plurality of second openings. Electrodes and traces are positioned inside a peripheral portion of a body portion of the device and alongside the layer. At least one of the first openings is adjacent each of the electrodes to provide a pathway through which the electrode may provide electrical stimulation to the spinal cord. At least one of the second openings is adjacent each of the traces to provide a pathway through which the trace may receive electrical stimulation. At least one trace is connected to each electrode and configured to conduct electrical stimulation received by the trace(s) to the electrode.

Abstract: The invention provides a process for producing a substrate with a piercing aperture, the piercing aperture being formed by conducting dry etching from the side of a second surface opposite to a first surface of a substrate to the first surface, the process comprising, in the following order, the steps of (a) forming a groove around a region where the piercing aperture is formed in the first surface of the substrate, (b) forming an etch-stop layer in the region where the piercing aperture is formed in the first surface of the substrate and in the interior of the groove, and (c) forming the piercing aperture by conducting the dry etching from the side of the second surface.

Abstract: A suspension board with circuit includes a metal supporting board, an insulating layer formed on the metal supporting board, and a conductive pattern formed on the insulating layer and having a terminal portion connected to connecting terminals of a magnetic head mounted on a slider. A slider mounting region where the slider is disposed is defined, and a plurality of the terminal portions are spaced apart from each other in the slider mounting region, and in the metal supporting board, an opening which opens so as to expose the insulating layer where the terminal portions are disposed is formed at the slider mounting region.

Abstract: Disclosed are a plasma processing method and a plasma processing apparatus which collectively perform etching under the same etching conditions while suppressing a shape abnormality. The multilayer film material has a polysilicon layer, a first metal layer formed on the polysilicon layer, and a hard mask layer which contains a tungsten layer formed on the first metal layer. In the method, plasma is generated by a mixed gas of a chloride-containing gas which contains a compound containing chlorine and silicon, a compound containing chlorine and boron, or a compound containing chlorine and hydrogen, a chlorine-containing gas which contains chlorine, and a processing gas which contains carbon and fluorine, and the hard mask layer is used as an etching mask so as to perform the etching from a top surface of the first metal layer to a bottom surface of the polysilicon layer.

Abstract: A compliant micro device transfer head and head array are disclosed. In an embodiment a micro device transfer head includes a spring arm having integrated electrode leads that is deflectable into a space between a base substrate and the spring arm.

Abstract: A flexure for a suspension of a head gimbal assembly includes a substrate layer, a dielectric layer formed thereon, a conducting layer formed on the dielectric layer, and an insulating cover layer covered on the conducting layer, wherein at least one window is configured at a surface of the insulating cover layer thereby a portion of the conducting layer is exposed, and an antistatic adhesive is adhered to at least one side wall of the window and contacted with the conducting layer. The new structure of the flexure can avoid or eliminate electro-static discharges enduringly without dipping water. A head gimbal assembly and a disk drive unit with the same, a manufacturing method for the flexure are also disclosed.

Abstract: A process of fabricating a heat dissipation substrate is provided. A metal substrate having an upper surface, a lower surface, first recesses located on the upper surface and second recesses located on the lower surface is provided. The metal substrate is divided into carrier units and connecting units connecting the carrier units. A first and a second insulating materials are respectively filled into the first and the recesses. A first conductive layer is formed on the upper surface and the first insulating material. A second conductive layer is formed on the lower surface and the second insulating material. The first and the second conductive layers are patterned to form a first and a second patterned conductive layers. The first and the second insulating materials are taken as an etching mask to etch the connecting units of the metal substrate so as to form a plurality of individual heat dissipation substrates.

Abstract: A neural interface includes a first dielectric material having at least one first opening for a first electrical conducting material, a first electrical conducting material in the first opening, and at least one first interconnection trace electrical conducting material connected to the first electrical conducting material. A stiffening shank material is located adjacent the first dielectric material, the first electrical conducting material, and the first interconnection trace electrical conducting material.

Abstract: A method for manufacturing a package substrate is provided, including etching a substrate to form trenches each having a buffer portion, and forming a circuit in each of the trenches. The trenches are formed by etching instead of excimer laser to increase the aspect ratio of the trench, thereby solving the problem that the metallic layer is not thick enough and achieving a high yield of the circuit and a good process capability index.

Abstract: A method provides an EAMR transducer. The EAMR transducer is coupled with a laser and has an ABS configured to reside in proximity to a media during use. The method includes providing an NFT using an NFT mask. The NFT resides proximate to the ABS and focuses the laser energy onto the media. A portion of the NFT mask is removed, forming a heat sink mask covering part of the NFT. Optical material(s) are deposited, covering the heat sink mask and the NFT. The heat sink mask is removed, providing an aperture in the optical material(s). A heat sink corresponding to the aperture is provided. The heat sink bottom is thermally coupled with the NFT. A write pole for writing to the media and coil(s) for energizing the write pole are provided. The write pole has a bottom surface thermally coupled with the top surface of the heat sink.

Abstract: An electrostatically tunable magnetoelectric inductor including: a substrate; a piezoelectric layer; and a magnetoelectric structure comprising a first electrically conductive layer, a magnetic film layer, a second electrically conductive layer, and recesses formed so as to create at least one electrically conductive coil around the magnetic film layer; with a portion of the substrate removed so as to enhance deformation of the piezoelectric layer. Also disclosed is a method of making the same. This inductor displays a tunable inductance range of >5:1 while consuming less than 0.5 mJ of power in the process of tuning, does not require continual current to maintain tuning, and does not require complex mechanical components such as actuators or switches.

Abstract: A method of etching a glass substrate using an etchant that is reversibly activated to etch only in precise locations in which such etching is desired and is deactivated when outside of these locations. The method involves exposing a first side of the glass substrate to a mixture of chemical substances that includes a neutralized etchant that is photosensitive. The neutralized etchant is formed by reacting a neutralizer with an etchant. The method also includes transmitting light from a direction of a second side of the glass into the mixture of chemical substances. In response to exposure to this light, the etchant is reversibly released from a bond to the neutralizer to form the etchant on predetermined areas of the first side of the glass, wherein the predetermined areas are defined by the dimension of the light.

Abstract: A new and novel method utilizing current nano-technological processes for fabricating a range of micro-devices with significantly expanded capabilities, unique functionalities at microscopic levels, enhanced degree of flexibilities, reduced costs and improved performance in the fields of bioscience and medicine is disclosed in the within patent application. Micro-devices fabricated using the disclosed nano-technological techniques have significant improvements in many areas over the existing, conventional methods. Such improvements include, but are not limited to reduced overall costs, early disease detection, targeted drug delivery, targeted disease treatment and reduced degree of invasiveness in treatment. Compared with existing, conventional approaches, the said inventive approach disclosed in this patent application is much more microscopic, sensitive, accurate, precise, flexible and effective.

Abstract: Provided is a method of manufacturing a circuit which includes: (a) providing a substrate made of a conductive material; (b) etching a first surface of the substrate excluding a region in which at least one via is to be formed; (c) etching a region of the etched first surface of the substrate in which an insulated portion of a first circuit is to be formed; (d) stacking a first insulation layer in spaces formed by the etching performed in operations (b) and (c); and (e) grinding a second surface of the substrate to expose the first insulation layer outward along with the first circuit, thereby forming a circuit board.

Abstract: A substrate includes an iron-nickel alloy core or a cobalt-nickel ferrous alloy core, a chromium conversion coating on at least a portion of the core, and an insulating coating on the chromium conversion coating. A method of making a substrate includes: providing an iron-nickel alloy core or a cobalt-nickel ferrous alloy core, applying a chromium conversion coating on at least a portion of the core, and applying an insulating coating on the chromium conversion coating.

Abstract: Object is to provide an etching solution which generates less foam and can etch copper or copper alloy at high selectivity when used in a step of etching copper or copper alloy in an electronic substrate having both of copper or copper alloy and nickel. The etching solution to be used in a step of selectively etching copper or copper alloy in an electronic substrate having both of copper or copper alloy and nickel has, as essential components thereof, (A) a linear alkanolamine, (B) a chelating agent having an acid group in the molecule thereof, and (C) hydrogen peroxide.

Abstract: Metalized web substrate is wet etched in a reaction vessel by contacting with oxidizing and metal complexing agent to remove metal from unpatterned region. Following etching, substrate is rinsed, and rinse is at least partly recycled. Concentrations of oxidizing and metal complexing agents in the etchant bath are maintained by delivering replenishment feeds of each. Concentration of metal in the etchant bath is maintained by discharging some of the etchant bath. Replenishment rates of oxidizing and metal complexing agents and etchant removal rate are determined based at least in part on rate that metal etched from the substrate enters the etchant bath.

Abstract: The invention involves a flexible circuit electrode array device comprising: a polymer layer; wherein the polymer layer includes one or more metal traces, an electrode array; one or more bond pads; and the electrode array is located on the opposite side of the polymer layer. The invention further involves a method for backside processing of a flexible circuit electrode device, comprising: applying polymer film on a substrate; processing the front side; releasing the polymer film from substrate; flipping over the polymer film and fixing it onto the substrate; processing the backside; and final releasing of the polymer film from the substrate. The invention further involves a method for backside processing of a flexible circuit electrode device, comprising: processing the front side without releasing the polymer; processing the backside by sacrificial substrate method, or by laser drilling method; and releasing the polymer film from the substrate.

Abstract: A piezoelectric device prevents damage to a piezoelectric thin film caused by etching and the manufacturing cost of the piezoelectric device is reduced. On a surface of a support layer formed on a support substrate, an etching adjustment layer is formed. An etchant flows through etching windows to simultaneously form a through hole through which a portion of a sacrificial layer is exposed to a side of a piezoelectric thin film and an opening through which the etching adjustment layer, which is conductive with a lower electrode, is exposed to the side of the piezoelectric thin film. By making an etchant flow through the through hole, the sacrificial layer is removed. A lead-out wiring is formed between an upper electrode and a bump pad and a lead-out wiring is formed between the conductive etching adjustment layer, which is conductive with the lower electrode, and a bump pad.

Abstract: A process for fabricating a nanochannel system using a combination of microelectromechanical system (MEMS) microfabrication techniques, atomic force microscopy (AFM) nanolithography, and focused ion beam (FIB). The nanochannel system, fabricated on either a glass or silicon substrate, has channel heights and widths on the order of single to tens of nanometers. The channel length is in the micrometer range. The nanochannel system is equipped with embedded micro and nanoscale electrodes, positioned along the length of the nanochannel for electron tunneling based characterization of nanoscale particles in the channel. Anodic bonding is used to cap off the nanochannel with a cover chip.

Abstract: A method for making a thermionic electron emission device. The method includes the following steps. First, an insulating substrate is provided. Second, a number of lattices are formed on the insulating substrate. Third, a first electrode and a second electrode are fabricated in each lattice on the insulating substrate. Fourth, a carbon nanotube film structure is provided and at least part of the carbon nanotube film is suspended structure above the insulating substrate. Sixth, excess carbon nanotube film structure is cut away to obtain a number of thermionic electron emitters. The thermionic electron emitters are spaced from each other and located between the first electrode and the second electrode in each lattice.

Abstract: A pattern generator includes a minor array plate having a mirror, at least one electrode plate disposed over the minor array plate, a lens let disposed over the minor, and at least one insulator layer sandwiched between the mirror array plate and the electrode plate. The electrode plate includes a first conducting layer and a second conducting layer. The lens let has a non-straight sidewall formed in the electrode plate. The pattern generator further includes at least one insulator sandwiched between two electrode plates. The non-straight sidewall can be a U-shaped sidewall or an L-shaped sidewall.

Abstract: The present disclosure relates to a method of fabricating a capacitive touch pane where a plurality of groups of first conductive patterns are formed along a first direction, a plurality of groups of second conductive patterns are formed along a second direction, and a plurality of connection components are formed on a substrate. Each first conductive pattern is electrically connected to another adjacent first conductive pattern in the same group by each connection component and each group of the second conductive patterns is interlaced with and insulated from each group of the first conductive patterns. Next, a plurality of curved insulation mounds are formed to cover the first connection components. Then, a plurality of bridge components are formed to electrically connect each second conductive pattern with another adjacent second conductive pattern in the same group.

Abstract: A method includes forming a chemical guide layer above a process layer. A template having a plurality of elements is formed above the process layer. The chemical guide layer is disposed on at least portions of the process layer disposed between adjacent elements of the template. A directed self-assembly layer is formed over the chemical guide layer. The directed self-assembly layer has alternating etchable components and etch-resistant components. The etchable components of the directed self-assembly layer are removed. The process layer is patterned using the template and the etch-resistant components of the directed self-assembly layer as an etch mask.

Abstract: Methods and structures are provided for implementing embedded hybrid electrical-optical printed circuit board (PCB) constructs. The embedded hybrid electrical-optical PCB construct includes electrical channels and optical channels within a single physical PCB layer. The embedded hybrid electrical-optical PCB construct includes an electrically conductive sheet or a copper sheet, and a reflective mesh adhesive layer provided with the electrical channels and optical channels within the single physical PCB layer.

Abstract: Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.

Abstract: Methods for fabricating templates for nanoelement assembly and methods for fluid-guided assembly of nanoelements are provided. Templates are fabricated by plasma modification of surface hydrophilicity and production of a network of hydrophobic trenches having a hydrophilic bottom surface. Single-walled carbon nanotubes (SWNT) can be assembled into stable films, ribbons, and wires of nanoscale thickness and nanoscale or microscale width and length. The nanofilm assemblies prepared according to the invention are highly conductive and can be used in the fabrication of a wide variety of microscale and nanoscale electronic devices.