Light Responsive Pn Junction Patents (Class 257/461)
  • Publication number: 20150084151
    Abstract: A photoelectric conversion element includes a first electrode, a ferroelectric layer provided on the first electrode, and a second electrode provided on the ferroelectric layer, the second electrode being a transparent electrode, and a pn junction being formed between the ferroelectric layer and the first electrode or the second electrode.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 26, 2015
    Inventors: Takayuki YONEMURA, Yoshihiko YOKOYAMA, Yasuaki HAMADA
  • Patent number: 8987738
    Abstract: A photoelectric conversion device with improved electric characteristics is provided. The photoelectric conversion device has a structure in which a window layer is formed by a stack of a first silicon semiconductor layer and a second silicon semiconductor layer, and the second silicon semiconductor layer has high carrier concentration than the first silicon semiconductor layer and has an opening. Light irradiation is performed on the first silicon semiconductor layer through the opening without passing through the second silicon semiconductor layer; thus, light absorption loss in the window layer can be reduced.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Hirose, Naoto Kusumoto
  • Patent number: 8962376
    Abstract: An optoelectronic device, including a semiconductor body having a surface to receive photons and a plurality of doped regions of opposite doping polarities, the doped regions extending substantially from the surface of the semiconductor body and into the semiconductor body, and being arranged in one or more pairs of opposite doping polarities such that each pair of doped regions forms a corresponding space charge region having a corresponding electric field therein, the space charge region extending substantially from the surface of the semiconductor body and into the semiconductor body such that photons entering the semiconductor body through the surface and travelling along paths within the space charge region generate electron-hole pairs in the space charge region that are separated in opposing directions substantially orthogonal to the photon paths by the electric field and collected by the corresponding pair of doped regions, thereby providing an electrical current to be conducted from the device.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: February 24, 2015
    Assignee: The Silanna Group Pty Ltd
    Inventors: Petar Branko Atanackovic, Steven Grant Duvall
  • Patent number: 8928107
    Abstract: Provided are light detection devices and methods of manufacturing the same. The light detection device includes a first conductive pattern on a surface of a substrate, an insulating pattern on the substrate and having an opening exposing at least a portion of the first conductive pattern, a light absorbing layer filling the opening of the insulating pattern and having a top surface disposed at a level substantially higher than a top surface of the insulating pattern, a second conductive pattern on the light absorbing layer, and connecting terminals electrically connected to the first and second conductive patterns, respectively.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: January 6, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Hoon Kim, Gyungock Kim, In Gyoo Kim, JiHo Joo, Ki Seok Jang
  • Publication number: 20140374867
    Abstract: Described herein is a pinned photodiode pixel architecture having a p-type substrate that is independently biased with respect to a pixel area to provide an avalanche region between an n-type region and a p-type region formed on the substrate. Such a pinned photodiode pixel can be used in imaging sensors that are used in low light level conditions.
    Type: Application
    Filed: June 19, 2014
    Publication date: December 25, 2014
    Applicants: IMEC VZW
    Inventors: Koen De Munck, Tomislav Resetar
  • Patent number: 8916945
    Abstract: Prepared is an n? type semiconductor substrate 1 having a first principal surface 1a and a second principal surface 1b opposed to each other, and having a p+ type semiconductor region 3 formed on the first principal surface 1a side. At least a region opposed to the p+ type semiconductor region 3 in the second principal surface 1b of the n? type semiconductor substrate 1 is irradiated with a pulsed laser beam to form an irregular asperity 10. After formation of the irregular asperity 10, an accumulation layer 11 with an impurity concentration higher than that of the n? type semiconductor substrate 1 is formed on the second principal surface 1b side of the n type semiconductor substrate 1. After formation of the accumulation layer 11, the n? type semiconductor substrate 1 is subjected to a thermal treatment.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: December 23, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Akira Sakamoto, Takashi Iida, Koei Yamamoto, Kazuhisa Yamamura, Terumasa Nagano
  • Patent number: 8912579
    Abstract: A solid-state image pickup device includes: a photoelectric conversion portion formed on a substrate and composed of a photodiode; an image pickup area in which plural pixels each including a reading-out electrode for reading out signal electric charges generated and accumulated in the photoelectric conversion portion are formed; and a light blocking film having an opening portion right above the photoelectric conversion portion in an effective pixel area of the image pickup area, and light-blocking said photoelectric conversion portion in an OB pixel area of the image pickup area, in which a film deposited between the light blocking film and the substrate right above the photoelectric conversion portion in the OB pixel area is composed of only a silicon oxide film.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: December 16, 2014
    Assignee: Sony Corporation
    Inventor: Kaori Takimoto
  • Patent number: 8912616
    Abstract: A photodiode device including a photosensitive diffusion junction within a single layer. The photodiode device further includes a resonant grating located within the single layer. The photosensitive diffusion junction is located within the resonant grating.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporaion
    Inventors: Matthias Fertig, Thomas Morf, Nkolaj Moll, Martin Kreissig, Karl-Heinz Brenner, Maximilian Auer
  • Patent number: 8912619
    Abstract: The present invention provides an ultra-violet light sensing device. The ultra-violet light sensing device includes a first conductivity type substrate, a second conductivity type region, and a first conductivity type high density region. The first conductivity type substrate includes a light incident surface. The second conductivity type region is disposed in the first conductivity type substrate and adjacent to the light incident surface. The first conductivity type high density region is disposed under the second conductivity type region. The present invention also provides another ultra-violet light sensing device, which further includes a first conductivity type high density shallow region which is sandwiched between the light incident surface and the second conductivity type region. Manufacturing methods for these ultra-violet light sensing devices are also disclosed in the present invention.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: December 16, 2014
    Assignee: Pixart Imaging Incorporation
    Inventors: Han-Chi Liu, Huan-Kun Pan, Eiichi Okamoto
  • Publication number: 20140353469
    Abstract: The present technology provides a semiconductor device that includes a substrate including an active region and an device isolation region, a plurality of micro insulation structures formed in the substrate of the device isolation region and spaced from each other, and an impurity region suitable for filling spaces between the micro insulation structures and for surrounding the micro insulation structures in the substrate of the device isolation region, and a method of fabricating the semiconductor device by improving a method of forming device isolation regions that insulate active regions. In particular, discontinuous micro insulation structures are suggested.
    Type: Application
    Filed: October 17, 2013
    Publication date: December 4, 2014
    Applicant: SK hynix Inc.
    Inventors: Do-Hyung KIM, Jang-Won MOON, Youn-Sub LIM, Do-Hwan KIM
  • Patent number: 8901697
    Abstract: An integrated circuit having an insulated conductor or within a semiconductor substrate and extending perpendicular to a plane of a semiconductor wafer or substrate on which the integrated circuit is fabricated, the conductor comprising a first region of doped semiconductor extending between a first device or a first contact and a second device or a second contact.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: December 2, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Bernard Patrick Stenson
  • Patent number: 8890219
    Abstract: An image sensor device is provided, including at least one transistor lying on a semiconductor-on-insulator substrate that includes a semi-conducting layer, in which a channel area of the transistor is disposed in a portion thereof, and an insulating layer separating the semi-conducting layer from a semi-conducting support layer, wherein the semi-conducting layer and the insulating layer extend beyond the channel area, and extend under at least a portion of source/drain regions of the transistor, wherein the semi-conducting support layer includes at least one photosensitive area including at least one P-doped region and at least one N-doped region forming a junction, the photosensitive area being disposed facing the transistor on a side of the channel area thereof and opposite a side of a gate electrode thereof, and wherein the insulating layer is configured to provide a capacitive coupling between the photosensitive area and the semi-conducting layer.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: November 18, 2014
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Laurent Grenouillet, Maud Vinet
  • Patent number: 8890275
    Abstract: The invention discloses an optoelectronic device and method of fabricating the same. The optoelectronic device according to the invention includes a semiconductor structure combination, a first surface passivation layer formed on an upper surface of the semiconductor structure combination, and a second surface passivation layer formed on the first surface passivation layer. The semiconductor structure combination includes at least one P-N junction. In particular, the interfacial state density of the first surface passivation layer is lower than that of the second surface passivation layer, and the fixed oxide charge density of the second surface passivation layer is higher than that of the first surface passivation layer.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: November 18, 2014
    Assignee: Sino-American Silicon Products Inc.
    Inventors: Miin-Jang Chen, Hsin-Jui Chen, Wen-Ching Hsu
  • Patent number: 8889536
    Abstract: A method is provided for forming a dopant profile based on a surface of a wafer-like semiconductor component with phosphorus as a dopant. The method includes the steps of applying a phosphorus dopant source onto the surface, forming a first dopant profile with the dopant source that is present on the surface, removing the dopant source, and forming a second dopant profile that has a greater depth in comparison to the first dopant profile. In order to form an optimized dopant profile, the dopant source is removed after forming the first dopant profile, and precipitates that are crystallized selectively on or in the surface from the precipitates SixPy and SixPyOz are removed.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: November 18, 2014
    Assignee: Schott Solar AG
    Inventors: Gabriele Blendin, Joerg Horzel, Agata Lachowicz, Berthold Schum
  • Publication number: 20140327102
    Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. A contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. The first polarity charge layer is disposed between a first one of a plurality of passivation layers and a second one of the plurality of passivation layers disposed over the photodiode region.
    Type: Application
    Filed: July 15, 2014
    Publication date: November 6, 2014
    Inventors: Howard E. Rhodes, Dajiang Yang, Gang Chen, Duli Mao, Vincent Venezia
  • Patent number: 8878053
    Abstract: A bipolar solar cell includes a backside junction formed by an N-type silicon substrate and a P-type polysilicon emitter formed on the backside of the solar cell. An antireflection layer may be formed on a textured front surface of the silicon substrate. A negative polarity metal contact on the front side of the solar cell makes an electrical connection to the substrate, while a positive polarity metal contact on the backside of the solar cell makes an electrical connection to the polysilicon emitter. An external electrical circuit may be connected to the negative and positive metal contacts to be powered by the solar cell. The positive polarity metal contact may form an infrared reflecting layer with an underlying dielectric layer for increased solar radiation collection.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: November 4, 2014
    Assignee: SunPower Corporation
    Inventor: Peter John Cousins
  • Patent number: 8872301
    Abstract: The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Yang Hung, Po-Zen Chen, Szu-Hung Yang, Chih-Cherng Jeng, Chih-Kang Chao, I-I Cheng
  • Publication number: 20140312446
    Abstract: A semiconducting structure configured to receive electromagnetic radiation and transform the received electromagnetic radiation into an electric signal, the semiconductor structure including a semiconducting support within a first surface defining a longitudinal plane, a first zone with a first type of conductivity formed in the support with a second zone with a second type of conductivity that is opposite of the first type of conductivity to form a semiconducting junction. A mechanism limiting lateral current includes a third zone formed in the support in lateral contact with the second zone, the third zone having the second type of conductivity for which majority carriers are electrons. The third zone has a sufficient concentration of majority carriers to have an increase in an apparent gap due to a Moss-Burstein effect.
    Type: Application
    Filed: November 27, 2012
    Publication date: October 23, 2014
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Olivier Gravrand, Gerard Destefanis
  • Patent number: 8859310
    Abstract: Methods of fabricating optoelectronic devices, such as photovoltaic cells and light-emitting devices. In one embodiment, such a method includes providing a substrate, applying a monolayer of semiconductor particles to the substrate, and encasing the monolayer with one or more coatings so as to form an encased-particle layer. At some point during the method, the substrate is removed so as to expose the reverse side of the encased-particle layer and further processing is performed on the reverse side. When a device made using such a method has been completed and installed into an electrical circuit the semiconductor particles actively participate in the photoelectric effect or generation of light, depending on the type of device.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: October 14, 2014
    Assignee: Versatilis LLC
    Inventor: Ajaykumar R. Jain
  • Patent number: 8860101
    Abstract: A system and method for reducing cross-talk between photosensitive diodes is provided. In an embodiment an isolation region comprising a first concentration of dopants is located between the photosensitive diodes. The photosensitive diodes have a second concentration of dopants that is less than the first concentration of dopants, which helps to prevent diffusion from the photosensitive diodes to form a potential path for undesired cross-talk between the photosensitive diodes.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: October 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lan Fang Chang, Ching-Hwanq Su, Wei-Ming You, Chih-Cherng Jeng, Chih-Kang Chao, Fu-Sheng Guo
  • Publication number: 20140299892
    Abstract: An optoelectronic semiconductor structure (20) comprises an n-type semiconductor region (3); a p-type semiconductor region (1); a p-n junction formed between the n-type and p-type semiconductor regions; and an active region (2). According to the present invention, the optoelectronic semiconductor structure (20) is configured to transport, when in use, charge carriers between the active region (2) and each of the retype semiconductor region (3) and the p-type semiconductor region (1) through a single substantially planar boundary surface (9) of the active region.
    Type: Application
    Filed: August 24, 2011
    Publication date: October 9, 2014
    Inventors: Jani Oksanen, Jaakko Tulkki
  • Patent number: 8847346
    Abstract: A photoelectric conversion portion, a charge holding portion, a transfer portion, and a sense node are formed in a P-type well. The charge holding portion is configured to include an N-type semiconductor region, which is a first semiconductor region holding charges in a portion different from the photoelectric conversion portion. A P-type semiconductor region having a higher concentration than the P-type well is disposed under the N-type semiconductor region.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: September 30, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yusuke Onuki, Yuichiro Yamashita, Masahiro Kobayashi
  • Patent number: 8841158
    Abstract: A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: September 23, 2014
    Assignee: Sony Corporation
    Inventor: Shin Iwabuchi
  • Publication number: 20140264388
    Abstract: The present disclosure generally relates to systems and methods for producing and using Group-III nitride crystals that have enhanced or increase ultraviolet transparency in a range of wavelengths. The crystals may also be used in a number of UV optics and UV optical semiconductor devices.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Nitride Solutions Inc.
    Inventor: Nitride Solution Inc.
  • Patent number: 8835992
    Abstract: An electronic device and a method of fabricating the same are provided. The electronic device includes: a photodiode layer; a wiring layer formed on the first surface of the photodiode layer; a plurality of electrical contact pads formed on the wiring layer; a passivation layer formed on the wiring layer and the electrical contact pads; an antireflective layer formed on the second surface of the photodiode layer; a color filter layer formed on the antireflective layer; a dielectric layer formed on the antireflective layer and the color filter layer; and a microlens layer formed on the dielectric layer, allowing the color filter layer, the dielectric layer and the microlens layer to define an active region within which the electrical contact pads are positioned. As the electrical contact pads are positioned within the active region, an area of the substrate used for an inactive region can be eliminated.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: September 16, 2014
    Assignee: Unimicron Technology Corporation
    Inventors: Tzyy-Jang Tseng, Dyi-Chung Hu
  • Patent number: 8823127
    Abstract: A multijunction photovoltaic (PV) cell includes a bottom flexible substrate and a bottom metal layer located on the bottom flexible substrate. The multijunction photovoltaic cell also includes a semiconductor layer located on the bottom metal layer and a stack having a plurality of junctions located on the semiconductor layer, each of the plurality of junctions having a respective bandgap. The pluralities of junctions are ordered from the junction having the smallest bandgap being located on the substrate to the junction having the largest bandgap being located on top of the stack.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Norma Sosa Cortes, Keith E. Fogel, Devendra Sadana, Davood Shahrjerdi
  • Patent number: 8823125
    Abstract: A solid-state image pickup device includes a photoelectric conversion portion, a charge holding portion configured to include a first-conductivity-type first semiconductor region, and a transfer portion configured to include a transfer gate electrode that controls a potential between the charge holding portion and a sense node. The charge holding portion includes a control electrode. A second-conductivity-type second semiconductor region is disposed on a surface of a semiconductor region between the control electrode and the transfer gate electrode. A first-conductivity-type third semiconductor region is disposed under the second semiconductor region. The third semiconductor region is disposed at a deeper position than the first semiconductor region.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: September 2, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yusuke Onuki, Yuichiro Yamashita, Masahiro Kobayashi
  • Patent number: 8816464
    Abstract: The present invention is a photodiode and/or photodiode array, having a p+ diffused area that is smaller than the area of a mounted scintillator crystal, designed and manufactured with improved device characteristics, and more particularly, has relatively low dark current, low capacitance and improved signal-to-noise ratio characteristics. More specifically, the present invention is a photodiode and/or photodiode array that includes a metal shield for reflecting light back into a scintillator crystal, thus allowing for a relatively small p+ diffused area.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 26, 2014
    Assignee: OSI Optoelectronics, Inc.
    Inventors: Peter Steven Bui, Narayan Dass Taneja
  • Patent number: 8816465
    Abstract: An energy conversion and storage device includes an energy storage component (530, 601) including a first electrode (611) having a first plurality of channels (612) formed in a first region (615) of a first material (617), a second electrode (621) adjacent to but electrically isolated from the first electrode and having a second plurality of channels (622) formed in a first region (625) of a second material (627), and an electrolyte (650) within the first and second pluralities of channels. The first electrode forms a first interface (619) with the electrolyte and the second electrode forms a second interface (629) with the electrolyte. The energy conversion and storage device further includes a photovoltaic component (520, 602) formed in a second region of the first material.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: August 26, 2014
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Cary L. Pint
  • Patent number: 8816462
    Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. The second polarity is opposite from the first polarity. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. An contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. A passivation layer is also disposed over the photodiode region between the pinning surface layer and the contact etch stop layer.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: August 26, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Howard E. Rhodes, Dajiang Yang, Gang Chen, Duli Mao, Vincent Venezia
  • Patent number: 8816459
    Abstract: An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: August 26, 2014
    Assignee: Siliconfile Technologies Inc.
    Inventors: In-Gyun Jeon, Se-Jung Oh, Heui-Gyun Ahn, Jun-Ho Won
  • Publication number: 20140231951
    Abstract: Provided is a structure of a silicon photomultiplier including an insulating layer to isolate pixels in the silicon photomultiplier and a quench resistor formed on the insulating layer to maximize the size of a light-receiving area, and a method of manufacturing the silicon photomultiplier.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 21, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Yong Sun YOON, Ji Eun LIM, Han Young YU, Won Ick JANG
  • Patent number: 8803272
    Abstract: A semiconductor device includes: a P-type semiconductor substrate; a first P-type semiconductor layer formed on the P-type semiconductor substrate; a second P-type semiconductor layer formed on the first P-type semiconductor layer and having a lower P-type impurity concentration than the first P-type semiconductor layer; an N-type semiconductor layer, which will form a cathode region, formed on the second P-type semiconductor layer; a first P-type diffusion layer formed by diffusing a P-type impurity in a partial region of the second P-type semiconductor layer; a second P-type diffusion layer formed by diffusing a P-type impurity in the second P-type semiconductor layer so as to be present adjacently beneath the first P-type diffusion layer at a lower P-type impurity concentration than the first P-type diffusion layer; and a photodiode formed in such a manner that the N-type semiconductor layer and the first P-type diffusion layer are isolated from each other.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: August 12, 2014
    Assignee: Sony Corporation
    Inventors: Hiroshi Yumoto, Shuji Yoneda, Tomokazu Mukai, Katsuhiko Takeuchi
  • Patent number: 8802472
    Abstract: A pixel and a pixel array of an image sensor device of the present invention have small pixel sizes by resetting sensed charge using a diode built vertically above a substrate. The pixel and the pixel array also have low noise performance by using a JFET as a source follower transistor for sensing charge. The pixel includes a floating diffusion node configured to sense photo-generated charge, a reset diode configured to reset the floating diffusion node in response to a reset signal, and a junction field effect transistor configured to output a signal having an output voltage level corresponding to a charge level of the floating diffusion node.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: August 12, 2014
    Assignee: Intellectual Ventures II LLC
    Inventor: Jaroslav Hynecek
  • Patent number: 8803273
    Abstract: A high sensitivity image sensor including a pixel, the pixel including a single electron field effect transistor (SEFET), the SEFET including a first conductive type well in a second conductive type substrate, second conductive type source and drain regions in the well and a first conductive type gate region in the well between the source and the drain regions.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: August 12, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eric R. Fossum, Dae-Kil Cha, Young-Gu Jin, Yoon-Dong Park, Soo-Jung Hwang
  • Publication number: 20140217540
    Abstract: A fully depleted “diode passivation active passivation architecture” (DPAPA) produces a photodiode structure which includes a substrate, a highly-doped buffer layer of a first carrier doping type above the substrate, a low-doped or undoped semiconductor active layer of the first carrier doping type above the buffer layer, a low-doped or undoped passivation layer above the active layer, the passivation layer having a wider band gap than the active layer; and a junction layer of a carrier doping type opposite the first carrier doping type above the passivation layer such that a pn junction is formed between the junction layer and the passivation and active layers, the junction creating a depletion region which expands completely through the passivation and active layers in response to a reverse bias voltage. The fully depleted structure substantially eliminates Auger recombination, reduces dark currents and enables cryogenic level performance at high temperatures.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 7, 2014
    Applicant: TELEDYNE SCIENTIFIC & IMAGING, LLC
    Inventors: WILLIAM E. TENNANT, DONALD L. LEE, ERIC C. PIQUETTE
  • Patent number: 8796804
    Abstract: An integrated circuit structure includes a substrate and a metallization layer over the substrate. The metallization layer includes a dielectric layer and metal lines in the dielectric layer. The integrated circuit structure further includes a sensing element over the metallization layer. The sensing element may be formed in passivation layers.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ke Chun Liu, Kuan-Chieh Huang, Chin-Min Lin, Ken Wen-Chien Fu, Mingo Lin
  • Patent number: 8796750
    Abstract: This invention comprises plurality of edge illuminated photodiodes. More specifically, the photodiodes of the present invention comprise novel structures designed to minimize reductions in responsivity due to edge surface recombination and improve quantum efficiency. The novel structures include, but are not limited to, angled facets, textured surface regions, and appropriately doped edge regions.
    Type: Grant
    Filed: November 11, 2012
    Date of Patent: August 5, 2014
    Assignee: OSI Optoelectronics, Inc.
    Inventors: Peter Steven Bui, Narayan Dass Taneja, Manoocher Mansouri
  • Patent number: 8791542
    Abstract: According to an embodiment, a solid-state imaging device includes a photoelectric, conversion element. The photoelectric conversion element includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. In the solid-state imaging device, D2m3/L2m3×ni32/N2<D1M2/L1M2×ni22/N2 and D1m1/L1m1×ni12/N1<D1m2/L1m2×ni22/N1 are established.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Toriyama, Koichi Kokubun, Hiroki Sasaki
  • Patent number: 8791538
    Abstract: A light receiving region includes a plurality of light detecting sections 10. The light detecting sections 10 has a second contact electrode 4A. The second contact electrode 4A is arranged at a position overlapping a first contact electrode 3A, so as to contact the first contact electrode. Further, a resistive layer 4B is continued to the second contact electrode 4A.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: July 29, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Koei Yamamoto, Terumasa Nagano, Kazuhisa Yamamura, Kenichi Sato, Ryutaro Tsuchiya
  • Patent number: 8785983
    Abstract: A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: July 22, 2014
    Assignee: Sony Corporation
    Inventors: Takayuki Ezaki, Teruo Hirayama
  • Patent number: 8785991
    Abstract: A solid state imaging device includes a photoelectric conversion portion in which the shape of potential is provided such that charge is mainly accumulated in a vertical direction.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: July 22, 2014
    Assignee: Sony Corporation
    Inventor: Keiji Mabuchi
  • Patent number: 8778787
    Abstract: Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: July 15, 2014
    Assignee: SunPower Corporation
    Inventor: Jane Manning
  • Patent number: 8779467
    Abstract: To provide a light emitting device high in reliability with a pixel portion having high definition with a large screen. According to a light emitting device of the present invention, on an insulator (24) provided between pixel electrodes. an auxiliary electrode (21) made of a metal film is formed, whereby a conductive layer (20) made of a transparent conductive film in contact with the auxiliary electrode can be made low in resistance and thin. Also, the auxiliary electrode (21) is used to achieve connection with an electrode on a lower layer, whereby the electrode can be led out with the transparent conductive film formed on an EL layer. Further, a protective film (32) made of a film containing hydrogen and a silicon nitride film which are laminated is formed, whereby high reliability can be achieved.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masaaki Hiroki, Masakazu Murakami, Hideaki Kuwabara
  • Patent number: 8772078
    Abstract: A method for laser separation of a thin film structure with multi junction photovoltaic materials. The method includes providing an optically transparent substrate having a thickness, a back surface region, and a front surface region including an edge region. The method further includes forming a thin film structure including a conductive layer on the optical transparent substrate. The conductive layer immediately overlies the front surface region. Additionally, the method includes aligning a laser beam with a beam spot on a first portion of the edge region from the back surface region through the thickness of the optically transparent substrate. The method further includes subjecting at least partially the conductive layer overlying the first portion via absorbed energy from the laser beam to separate an edge portion of the thin film structure from the first portion of the edge region.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: July 8, 2014
    Assignee: Stion Corporation
    Inventor: Chester A. Farris, III
  • Patent number: 8766393
    Abstract: A photodetector is formed from a body of semiconductor material substantially surrounded by dielectric surfaces. A passivation process is applied to at least one surface to reduce the rate of carrier generation and recombination on that surface. Photocurrent is read out from at least one electrical contact, which is formed on a doped region whose surface lies entirely on a passivated surface. Unwanted leakage current from un-passivated surfaces is reduced through one of the following methods: (a) The un-passivated surface is separated from the photo-collecting contact by at least two junctions; (b) The un-passivated surface is doped to a very high level, at least equal to the conduction band or valence band density of states of the semiconductor; (c) An accumulation or inversion layer is formed on the un-passivated surface by the application of an electric field.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: July 1, 2014
    Assignee: Infrared Newco, Inc.
    Inventors: Conor S. Rafferty, Clifford A. King
  • Patent number: 8759814
    Abstract: A semiconductor light-emitting device and a manufacturing method thereof are provided, wherein the semiconductor light-emitting device includes a first type doped semiconductor structure, a light-emitting layer, a second type doped semiconductor layer, a first conductive layer and a dielectric layer. The first type doped semiconductor structure includes a base and a plurality of columns extending outward from the base. Each of the columns includes a top surface and a plurality of sidewall surfaces. The light-emitting layer is disposed on the sidewall surfaces and the top surface, wherein the surface area of the light-emitting layer gradually changes from one side adjacent to the columns to a side away from the columns. The dielectric layer exposes the first conductive layer locating on the top surface of each of the columns, wherein the dielectric layer includes at least one of a plurality of quantum dots, phosphors, and metal nanoparticles.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 24, 2014
    Assignee: National Taiwan University
    Inventors: Chih-Chung Yang, Che-Hao Liao, Shao-Ying Ting, Horng-Shyang Chen, Wen-Ming Chang, Yu-Feng Yao, Chih-Yen Chen, Hao-Tsung Chen
  • Patent number: 8759886
    Abstract: A solid-state image capturing device including: a substrate; a substrate voltage source which applies a first potential to the substrate during a light reception period and applies a second potential to the substrate during a non-light reception period; and a plurality of pixels which each includes a light receiver which is formed on a front surface of the substrate and generates signal charges in accordance with received light, a storage capacitor which is formed adjacent to the light receiver and accumulates and stores signal charges generated by the light receiver, dark-current suppressors which are formed in the light receiver and the storage capacitor, an electronic shutter adjusting layer which is formed in an area facing the light receiver in the substrate and distant from the storage capacitor and which adjusts potential distribution, and a floating diffusion portion to which the signal charges accumulated in the storage capacitor are transmitted.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: June 24, 2014
    Assignee: Sony Corporation
    Inventor: Hideo Kanbe
  • Patent number: 8741681
    Abstract: A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation diffusion layer, wherein a charge accumulation region is disposed in the well region surrounded by the first and second isolation diffusion layers, the inner peripheral part of the first isolation diffusion layer forms a projecting region, an impurity having a conductivity type of the first isolation diffusion layer and an impurity having a conductivity type of the charge accumulation region are mixed in the projecting region, and a part of the charge accumulation region between the charge accumulation region and the second isolation diffusion layer is abutted or close to the second isolation diffusion layer under the projecting region.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: June 3, 2014
    Assignee: Sony Corporation
    Inventors: Keiji Tatani, Hideshi Abe, Masanori Ohashi, Atsushi Masagaki, Atsuhiko Yamamoto, Masakazu Furukawa
  • Patent number: 8742543
    Abstract: The invention is directed to an avalanche photodiode containing a substrate and semiconductor layers with various electro-physical properties having common interfaces both between themselves and with the substrate. The avalanche photodiode may be characterized by the presence in the device of at least one matrix consisting of separate solid-state areas with enhanced conductivity surrounded by semiconductor material with the same type of conductivity. The solid-state areas are located between two additional semiconductor layers, which have higher conductivity in comparison to the semiconductor layers with which they have common interfaces. The solid-state areas are generally made of the same material as the semiconductor layers surrounding them but with conductivity type that is opposite with respect to them. The solid-state areas may be made of a semiconductor with a narrow forbidden zone with respect to the semiconductor layers with which they have common interfaces.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: June 3, 2014
    Inventors: Ziraddin Yagub-Ogly Sadygov, Abdelmounairne Faouzi Zerrouk