Device Sensitive To Infrared, Visible, Or Ultraviolet Radiation (epo) Patents (Class 257/E31.054)

  • Publication number: 20080157252
    Abstract: The invention provides an optical sensor package. The package comprises a circuit board, an image sensor module and a packaging cap. The image sensor module electrically connects to the circuit board; the packaging cap is mounted on the circuit board and integrally packages the image sensor module. Hereby, the new architecture of the invention is not complex and its volume is small. The cost of the package is low, and the invention has the functions of electrostatic discharge and waterproofing; besides, the packaging cap can integrally package the image sensor module and a light-emitting module.
    Type: Application
    Filed: December 13, 2007
    Publication date: July 3, 2008
    Applicant: LITE-ON SEMICONDUCTOR CORP.
    Inventors: Chia-Chu Cheng, Tzu-Heng Liu, Wei-Chih Hsu, Kun-Hsun Lee
  • Publication number: 20080157152
    Abstract: The embodiment relates to a complementary metal oxide semiconductor (CMOS) image sensor and more particularly, to a CMOS image sensor and a manufacturing method thereof capable of improving electron storing capacity in a floating diffusion area. The CMOS image sensor includes a first gate electrode on a semiconductor substrate; a photodiode in the semiconductor substrate on one side of the first gate electrode; a floating diffusion area in the semiconductor substrate on an opposite side of the first gate electrode; a capacitor including a lower capacitor electrode connected to the floating diffusion area, a dielectric layer on the lower capacitor electrode, and an upper capacitor electrode; a drive capacitor coupled to the lower capacitor electrode and having a second gate electrode connected to the floating diffusion area. The electron storing capacity of the floating diffusion node is increased, making it possible to improve the dynamic range of the image sensor.
    Type: Application
    Filed: December 21, 2007
    Publication date: July 3, 2008
    Inventor: Hee Sung Shim
  • Publication number: 20080149975
    Abstract: A method of manufacturing an image sensor that may restrain the oxidization of a pad. A method of manufacturing an image sensor may include at least one of the following steps: Forming a photodiode structure including a pixel in an active region of a semiconductor substrate. Forming a conductive pad electrically connected the pixel in a peripheral region of the semiconductor substrate, where the peripheral region at least partially surrounds the active region. Forming a passivation layer with an opening exposing the pad on and/or over the photodiode structure. Covering the exposed pad with an etching prevention layer. Forming a color filter on and/or over the passivation layer corresponding to the pixel. Forming a microlens on and/or over the color filter. Removing the etching prevention layer from the pad.
    Type: Application
    Filed: November 20, 2007
    Publication date: June 26, 2008
    Inventor: In-Cheol Baek
  • Publication number: 20080142857
    Abstract: Embodiments relate to an image sensor and a method for manufacturing an image sensor that may prevent a photoresist pattern from remaining on gates by forming a floating diffusion area faster than the gates. According to embodiments, since the gates may not be influenced by an ion implantation process, current characteristics and operation reliability may be enhanced. According to embodiments, the method may include forming dummy ion implantation mask patterns for forming a floating diffusion area over an epitaxial layer and forming an ion implantation mask pattern over the epitaxial layer and at least a portion of the dummy ion implantation mask patterns, so as to form the floating diffusion area by performing an ion implantation process.
    Type: Application
    Filed: November 7, 2007
    Publication date: June 19, 2008
    Inventor: Jeong-Su Park
  • Patent number: 7372068
    Abstract: A QWIP structure is disclosed that includes a graded emitter barrier and can further be configured with a blocked superlattice miniband. The graded emitter barrier effectively operates to launch dark electrons into the active quantum well region, thereby improving responsivity. A graded collector barrier may also be included for reverse bias applications. The configuration operates to eliminate or otherwise reduce image artifacts or persistence associated with dielectric relaxation effect in low-background applications.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: May 13, 2008
    Assignee: Bae Systems Information and Electronic Systems Integration Inc.
    Inventors: Mani Sundaram, Axel R Reisinger
  • Publication number: 20080105905
    Abstract: Provided are a high-quality CMOS image sensor and a photo diode, which can be fabricated in sub-90 nm regime using nanoscale CMOS technology. The photo diode includes: a p-type well; an internal n-type region formed under a surface of the p-type well; and a surface p-type region including a highly doped p-type SiGeC epitaxial layer or a polysilicon layer deposited on a top surface of the p-type well over the internal n-type region. The image sensor includes: a photo diode including an internal n-type region and a surface p-type region; a transfer transistor for transmitting photo-charges generated in the photo diode to a floating diffusion node; and a driving transistor for amplifying a variation in an electric potential of the floating diffusion node due to the photo-charges. The image sensor further includes a floating metal layer for functioning as the floating diffusion node and applying an electric potential from a drain of the transfer transistor to a gate of the driving transistor.
    Type: Application
    Filed: October 16, 2007
    Publication date: May 8, 2008
    Inventors: Jin KANG, Jin KOO, Sang LEE
  • Patent number: 7368762
    Abstract: The present invention provides a heterojunction photodiode which includes a pn or Schottky-barrier junction formed in a first material region having a bandgap energy Eg1. When reverse-biased, the junction creates a depletion region which expands towards a second material region having a bandgap energy Eg2 which is less than Eg1. This facilitates signal photocurrent generated in the second region to flow efficiently through the junction in the first region while minimizing the process-related dark currents and associated noise due to near junction defects and imperfect surfaces which typically reduce photodiode device performance. The heterojunction photodiode can be included in an imaging system which includes an array of junctions to form an imager.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: May 6, 2008
    Assignee: Teledyne Licensing, LLC
    Inventors: William E. Tennant, Eric C. Piquette, Donald L. Lee, Mason L. Thomas, Majid Zandian
  • Publication number: 20080099869
    Abstract: The present invention provides a two-dimensional image detecting apparatus including a mold structure which apparatus can be applied to mammography, and a manufacturing method thereof. The manufacturing method includes: a conversion layer formation step of forming a conversion layer (3) on an active matrix substrate (2); a counter substrate formation step of disposing a spacer material (5) and disposing the counter substrate (6) so as to be opposite to the active matrix substrate (2) via the spacer material (5); a mold resin layer formation step of forming a mold structure layer (8) in a space surrounded by the conversion layer (3), the spacer material (5), and the counter substrate (6); and a cutting step of cutting at least the active matrix substrate (2) so that cut surfaces of the constituent members are flush with each other; and a sealing step of securing a sealing material (7) to the cut surface.
    Type: Application
    Filed: October 18, 2005
    Publication date: May 1, 2008
    Inventor: Yoshihiro Izumi
  • Publication number: 20080064135
    Abstract: Embodiments relate to a method of manufacturing an image sensor which may include forming a gate pattern including a tunnel oxide film, an oxide-nitride-oxide (ONO) film, a floating gate and a control gate over a semiconductor substrate. An oxide film and a nitride film may be formed over the semiconductor substrate including the gate pattern. A photoresist pattern may be formed which covers the oxide film and the nitride film formed over the gate pattern. The nitride film may be etched in a region not covered by the photoresist pattern. The oxide film may be etched to have a predetermined thickness. A deep implant process may deeply implant an N-type dopant into the semiconductor substrate. Ashing and cleaning processes may remove the remaining photoresist pattern.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 13, 2008
    Inventor: Joo-Hyeon Lee
  • Patent number: 7304361
    Abstract: The present invention proposes an organic photovoltaic component, particularly an organic solar cell, whose electrode is implemented as unstructured and is provided with a passivation layer, so that the passivated electrode layer acts functionally as a structured electrode or electrode layer.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: December 4, 2007
    Assignee: Konarka Technologies, Inc.
    Inventors: Christoph Brabec, Pavel Schilinsky, Christoph Waldauf
  • Publication number: 20070190681
    Abstract: A method is provided for forming a near infrared (NIR) active pixel sensor array on a silicon-on-insulator (SOI) substrate. The method forms a first wafer comprising a high resistance first Si substrate and a moderately doped first Si layer, and forms a second wafer comprising a first silicon oxide layer and a second Si layer. The method bonds the first wafer to the second wafer, forming a SOI substrate. Then, a diode is formed with a p-n junction space charge region extending into the first Si substrate. A thin-film transistor (TFT) is formed in the second Si layer, and interconnects are formed between the TFT and the diode. For example, first Si substrate may have a resistivity of greater than 100 ohm-cm, and the first Si layer may have a dopant concentration in the range of about 1×1016 to about 5×1018 cm?3.
    Type: Application
    Filed: February 13, 2006
    Publication date: August 16, 2007
    Inventors: Jong-Jan Lee, Jer-Shen Maa, Douglas Tweet, Sheng Hsu
  • Patent number: 7250647
    Abstract: An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e, one-sided) active area extension region on one side of the transistor gate opposite the photoconversion device, while other transistors can have normal symmetrical (i.e, two-sided) active area extension regions (e.g., lightly doped drains) with resulting high performance and short gate lengths. The asymmetrical active area extension region of the transistor associated with the photodiode can serve to reduce dark current at the photoconversion device. The punch-through problem normally cured by a lightly doped drain is fixed at the transistor associated with the photoconversion device by adding a Vt adjustment implant and/or increasing its gate length.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: July 31, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Publication number: 20070132052
    Abstract: Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals.
    Type: Application
    Filed: August 24, 2006
    Publication date: June 14, 2007
    Applicant: Edward Sargent
    Inventors: Edward Sargent, Gerasimos Konstantatos, Larissa Levina, Ian Howard, Ethan Klem, Jason Clifford
  • Patent number: 7227246
    Abstract: An apparatus comprises a first substrate and a second substrate. The first substrate includes an optoelectronic device and a matching circuit. The second substrate includes a driver circuit. A frequency response of the optoelectronic device is changed by the matching circuits. The first substrate is coupled to the second substrate via respective bond pads from the first and second substrates such that the matching circuit is interposed between the optoelectronic device and the driver circuit.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: June 5, 2007
    Assignee: Avago Technologies Fiber IP (Singapore) Pte. Ltd.
    Inventor: Peter Henry Mahowald
  • Patent number: 7226803
    Abstract: A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5×1017 atoms per cm3 to about 1×1019 atoms per cm3. The ultra-shallow highly-doped surface layer is formed by diffusion of ions from a doped layer into the substrate or by a plasma doping process. The ultra-shallow pinned layer is in contact with a charge collection region of a second conductivity type.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: June 5, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Chandra Mouli, Howard E. Rhodes, Richard A. Mauritzson
  • Patent number: 7198976
    Abstract: Channel stop sections are formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate.
    Type: Grant
    Filed: November 11, 2003
    Date of Patent: April 3, 2007
    Assignee: Sony Corporation
    Inventor: Kiyoshi Hirata
  • Patent number: 7161220
    Abstract: A structure (and method for forming the structure) includes a photodetector, a substrate formed under the photodetector, and a barrier layer formed over the substrate. The buried barrier layer preferably includes a single or dual p-n junction, or a bubble layer for blocking or eliminating the slow photon-generated carriers in the region where the drift field is low.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: January 9, 2007
    Assignee: International Business Machines Corporation
    Inventors: Guy Moshe Cohen, Qiqing C. Ouyang, Jeremy Daniel Schaub
  • Patent number: 7151287
    Abstract: In one embodiment, an image sensor for an x-ray imager includes a photodiode and a readout circuit. A deep well formed below the readout circuit may be configured as a diode to drain away parasitic electrons, which would otherwise induce noise in images. The parasitic electrons may be drained away to a power supply or a measuring circuit for dosimetrie purposes, for example.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: December 19, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Danny Scheffer, Tom A. Walschap
  • Publication number: 20060231911
    Abstract: An imaging device comprises a select line, a first signal line crossing the select line, and a first pixel provided at a portion corresponding to a crossing portion of the select line and the first signal line, the first pixel comprising a first buffer layer formed on a substrate, a first bolometer film formed on the first buffer layer, made of a compound which undergoes metal-insulator transition, and generating a first temperature detection signal, a first switching element formed on the substrate, selected by a select signal from the select line, and supplying the first temperature detection signal to the first signal line, and a metal wiring connecting a top surface of the first bolometer film to the first switching element.
    Type: Application
    Filed: June 29, 2005
    Publication date: October 19, 2006
    Inventors: Sumio Ikegawa, Kohei Nakayama, Hideyuki Funaki, Yoshinori Iida, Keitaro Shigenaka
  • Patent number: 7102185
    Abstract: An interline transfer type image sensing device that can be operated at high speed and with low image smear is described. The device incorporates a refractory metal layer which is used for both a light shield over the vertical charge transfer region and as a wiring layer for low resistance strapping of poly crystalline silicon (polysilicon) gate electrodes for the vertical charge transfer region. Plugs provided by a separate metallization layer connect the refractory light shield to the polysilicon gate electrode. These plugs allow high temperature processing after refractory light shield patterning for improved sensor performance without degradation of the polysilicon gate electrode or the refractory lightshield layer.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: September 5, 2006
    Assignee: Eastman Kodak Company
    Inventors: David N. Nichols, David L. Losee, Christopher Parks