Abstract: It is prevented that when a predetermined number of semiconductor chips having transistors are manufactured from one semiconductor wafer, manufacturing cost of a semiconductor device is increased due to excess semiconductor chips manufactured from the semiconductor wafer. A first bipolar transistor including a first emitter region having a first area is formed in a first chip formation region in an exposure region that can be exposed by one exposure step, and a second bipolar transistor including a second emitter region having a second area different from the first area is formed in a second chip formation region in the exposure region.

Abstract: It is prevented that when a predetermined number of semiconductor chips having transistors are manufactured from one semiconductor wafer, manufacturing cost of a semiconductor device is increased due to excess semiconductor chips manufactured from the semiconductor wafer. A first bipolar transistor including a first emitter region having a first area is formed in a first chip formation region in an exposure region that can be exposed by one exposure step, and a second bipolar transistor including a second emitter region having a second area different from the first area is formed in a second chip formation region in the exposure region.

Abstract: A reverse conducting insulated gate bipolar transistor (IGBT) manufacturing method, comprising the following steps: providing a substrate having an IGBT structure formed on the front surface thereof; implanting P+ ions onto the back surface of the substrate; forming a channel on the back surface of the substrate through photolithography and etching processes; planarizing the back surface of the substrate through a laser scanning process to form P-type and N-type interval structures; and forming a back surface collector by conducting a back metalizing process on the back surface of the substrate. Laser scanning process can process only the back surface structure requiring annealing, thus solve the problem of the front surface structure of the reverse conducting IGBT restricting back surface annealing to a low temperature, improving the P-type and N-type impurity activation efficiency in the back surface structure of the reverse conducting IGBT, and enhancing the performance of the reverse conducting IGBT.

Abstract: A method for surface treatment is disclosed which relates to the technical field of producing thin-film devices by printing and solves the problem that the treatment of a substrate surface in the prior art can hardly meet the requirement for printing. The method for surface treatment includes a step of subjecting a surface of a base plate having at least two kinds of substrate patterns formed thereon to a surface treatment for forming a self-assembled monomolecular layer for at least once and a surface treatment by ultraviolet-ozone cleaning, so as to make the difference between the surface energies of the substrate patterns larger or smaller. The method for surface treatment of the invention is suitable for the surface treatment of the substrate surface during producing thin-film devices by printing.

Abstract: Embodiments of the invention relate generally to creating semiconductor junctions with reduced contact resistance. In one embodiment, the invention provides a method of forming a composition of material, the method comprising: providing at least two populations of semiconducting materials; layering the at least two populations of semiconducting materials to form at least two layers; and consolidating the at least two populations of semiconducting materials, wherein the consolidating creates an electrical connection between the at least two layers.

Abstract: The present invention provides improved methods of preparing a low-k dielectric material on a substrate. The methods involve multiple operation ultraviolet curing processes in which UV intensity, wafer substrate temperature, UV spectral distribution, and other conditions may be independently modulated in each operation. Operations may be pulsed or even be concurrently applied to the same wafer. In certain embodiments, a film containing a structure former and a porogen is exposed to UV radiation in a first operation to facilitate removal of the porogen and create a porous dielectric film. In a second operation, the film is exposed to UV radiation to increase cross-linking within the porous film.

Abstract: In the transistor including an oxide semiconductor film, which includes a film for capturing hydrogen from the oxide semiconductor film (a hydrogen capture film) and a film for diffusing hydrogen (a hydrogen permeable film), hydrogen is transferred from the oxide semiconductor film to the hydrogen capture film through the hydrogen permeable film by heat treatment. Specifically, a base film or a protective film of the transistor including an oxide semiconductor film has a stacked-layer structure of the hydrogen capture film and the hydrogen permeable film. At this time, the hydrogen permeable film is formed on a side which is in contact with the oxide semiconductor film. After that, hydrogen released from the oxide semiconductor film is transferred to the hydrogen capture film through the hydrogen permeable film by the heat treatment.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a base region and an emitter region in a front surface of a semiconductor layer. The method can include forming a first impurity implantation region by implanting first impurity of a first conductivity type into a back surface of the semiconductor layer. The method can include selectively forming a second impurity implantation region by selectively implanting second impurity of a second conductivity type into the first impurity implantation region. In addition, the method can include irradiating the first impurity implantation region and the second impurity implantation region with laser light. A peak of impurity concentration profile in a depth direction of at least one of the first impurity implantation region and the second impurity implantation region before irradiation with the laser light is adjusted to a depth of 0.05 ?m or more and 0.

Abstract: Embodiments of the invention relate generally to creating semiconductor junctions with reduced contact resistance. In one embodiment, the invention provides a method of forming a composition of material, the method comprising: providing at least two populations of semiconducting materials; layering the at least two populations of semiconducting materials to form at least two layers; and consolidating the at least two populations of semiconducting materials, wherein the consolidating creates an electrical connection between the at least two layers.

Abstract: The object of the present invention is to provide a method of fabricating a thermoelectric material and a thermoelectric material fabricated thereby. According to the present invention, since carbon nanotubes with no surface treatment are dispersed in the alloy, electrical resistivity decreases and electrical conductivity increases in comparison to surface-treated carbon nanotubes and an amount of thermal conductivity decreased is the same as that in the case of using surface-treated carbon nanotubes, and thus, a ZT value, a thermoelectric figure of merit, is improved. A separate reducing agent is not used and an organic solvent having reducing powder is used to improve economic factors related to material costs and process steps, and carbon nanotubes may be dispersed in the thermoelectric material without mechanical milling.

Abstract: Methods of forming an oxide material layer are provided. The method includes mixing a precursor material with a peroxide material to form a precursor solution, coating the precursor solution on a substrate, and baking the coated precursor solution.

Abstract: Wafer-level processing of wafer assemblies with transducers is described herein. A method in accordance with some embodiments includes forming a solid state transducer device by forming one or more trenches to define solid state radiation transducers. An etching media is delivered in to the trenches to release the transducers from a growth substrate used to fabricate the transducers. A pad can hold the radiation transducers and promote distribution of the etching media through the trenches to underetch and release the transducers.

Abstract: Provided is a forming device and method making it possible to obtain a low-temperature polysilicon film in which the size of crystal grains fluctuates minimally, and is uniform. A mask has laser-light-blocking areas and laser-light-transmission areas arranged in the form of a grid such that the light-blocking areas and transmission areas are not adjacent to one another. Laser light is directed by the microlenses through the masks to planned channel-area-formation areas. The laser light transmitted by the transmission areas is directed onto an a-Si:H film, annealing and polycrystallizing the irradiated parts thereof. The mask is then removed, and when the entire planned channel-area-formation area is irradiated with laser light, the already-polycrystallized area, having a higher melting point, does not melt, while the area in an amorphous state melts and solidifies, leading to polycrystallization.

Abstract: There is provided a method of producing a semiconductor wafer by thermally processing a base wafer having a portion to be thermally processed that is to be thermally processed. The method comprises a step of providing, on the base wafer, a portion to be heated that generates heat through absorption of an electromagnetic wave and selectively heats the portion to be thermally processed, a step of applying an electromagnetic wave to the base wafer, and a step of lowering the lattice defect density of the portion to be thermally processed, by means of the heat generated by the portion to be heated through the absorption of the electromagnetic wave.

Abstract: A method for making a semi-conductor nanocrystals, including at least the steps of: making a stack of at least one uniaxially stressed semi-conductor thin layer and a dielectric layer, annealing the semi-conductor thin layer such that a dewetting of the semi-conductor forms, on the dielectric layer, elongated shaped semi-conductor nanocrystals oriented perpendicularly to the stress axis.

Abstract: One illustrative method disclosed herein includes forming a plurality of die above a crystalline semiconducting substrate, irradiating and cooling an edge region of the substrate to form an amorphous region in the edge region of the substrate and, after forming the amorphous region, performing at least one process operation to reduce the thickness of the substrate.

Abstract: A method for making semi-conductor nanocrystals, including at least the steps of: forming solid carbon chemical species on a semi-conductor thin layer provided on at least one dielectric layer, the dimensions and the density of the carbon chemical species formed on the semi-conductor thin layer being a function of the desired dimensions and density of the semi-conductor nanocrystals; annealing the semi-conductor thin layer, performing a dewetting of the semi-conductor and forming, on the dielectric layer, the semi-conductor nanocrystals.

Abstract: The present invention addresses provides improved methods of preparing a low-k dielectric material on a substrate. The methods involve multiple operation ultraviolet curing processes in which UV intensity, wafer substrate temperature and other conditions may be independently modulated in each operation. In certain embodiments, a film containing a structure former and a porogen is exposed to UV radiation in a first operation to facilitate removal of the porogen and create a porous dielectric film. In a second operation, the film is exposed to UV radiation to increase cross-linking within the porous film. In certain embodiments, the curing takes place in a multi-station UV chamber wherein UV intensity and substrate temperature may be independently controlled at each station.

Abstract: A method of producing a thin film using plasma enhanced chemical vapor deposition, including the steps of supplying a cation species to a substrate region when there is at most a relatively low flux of a plasma based anion species in the substrate region, and supplying the plasma based anion species to the substrate region when there is at most a relatively low flux of the cation species in the substrate region. This enables delivery of gaseous reactants to be separated in time in PECVD and/or RPECVD based film growth systems, which provides a significant reduction in the formation of dust particles for these plasma based film growth techniques.

Abstract: Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.

Abstract: According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element.

Abstract: A method of forming a semiconductor device structure includes forming an interlevel dielectric (ILD) layer over a semiconductor substrate and a dummy transistor gate structure formed on the substrate; infusing a shallow gas cluster ion beam (GCIB) layer in a top portion of the ILD layer; and removing at least one layer from the dummy transistor gate structure, wherein the at least one layer comprises a same material as the ILD layer and wherein the GCIB layer has a slower etch rate with respect to the ILD layer.

Abstract: A method for controlling the threshold voltage of a semiconductor element having at least a semiconductor as a component is characterized in including a process to measure one of a threshold voltage and a characteristic value serving as an index for the threshold voltage; a process to determine one of the irradiation intensity, irradiation time, and wavelength of the light for irradiating the semiconductor based on one of the measured threshold voltage and the measured characteristic value serving as the index for the threshold voltage; and a process to irradiate light whose one of the irradiation intensity, irradiation time, and wavelength has been determined onto the semiconductor; wherein the light irradiating the semiconductor is a light having a longer wavelength than the wavelength of the absorption edge of the semiconductor, and the threshold voltage is changed by the irradiation of the light.

Abstract: An X-ray image sensor having scintillating material embedded into wave-guide structures fabricated in a CMOS image sensor (CIS). After the CIS has been fabricated, openings (deep pores) are formed in the back side of the CIS wafer. These openings terminate at a distance of about 1 to 5 microns below the upper silicon surface of the wafer. The depth of these openings can be controlled by stopping on a buried insulating layer, or by stopping on an epitaxial silicon layer having a distinctive doping concentration. The openings are aligned with corresponding photodiodes of the CIS. The openings may have a shape that narrows as approaching the photodiodes. A thin layer of a reflective material may be formed on the sidewalls of the openings, thereby improving the efficiency of the resulting waveguide structures. Scintillating material (e.g., CsI(Tl)) is introduced into the openings using a ForceFill™ technology or by mechanical pressing.

Abstract: An improved method of producing solar cells utilizes a mask which is fixed relative to an ion beam in an ion implanter. The ion beam is directed through a plurality of apertures in the mask toward a substrate. The substrate is moved at different speeds such that the substrate is exposed to an ion dose rate when the substrate is moved at a first scan rate and to a second ion dose rate when the substrate is moved at a second scan rate. By modifying the scan rate, various dose rates may be implanted on the substrate at corresponding substrate locations. This allows ion implantation to be used to provide precise doping profiles advantageous for manufacturing solar cells.

Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.

Abstract: A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.

Abstract: An ion implantation is performed to implant ions into a silicon substrate, and a microwave irradiation is performed to irradiate the silicon substrate with microwaves after the ion implantation. After the microwave irradiation, the silicon substrate is transferred to a heat-treatment apparatus, where the silicon substrate is treated with heat by being irradiated with light having a pulse width ranging from 0.1 milliseconds to 100 milliseconds, both inclusive.

Abstract: This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost.

Abstract: A method for manufacturing a semiconductor device according to the invention irradiates a first pulse laser beam with an irradiation energy density of 1.0 J/cm2 or higher to blow off particles on the surface of wafer in activating an impurity layer positioned at a shallow location from the surface of wafer such as p+-type collector layer in an FS-type IGBT or in an NPT-type IGBT. By irradiating a second laser beam, region, on which particles were, is activated in the same manner as the region, on which particles are not, and p+-type collector layer is formed uniformly. The manufacturing method according to the invention facilitates preventing nonuniform laser beam irradiation from causing in laser annealing and preventing defective devices from causing.

Abstract: In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM antifuse stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM antifuse stack. Other aspects are provided.

Abstract: A dual wavelength exposure system provides for patterning a resist layer formed on a wafer for forming semiconductor devices, using two exposure operations, one including a first radiation having a first wavelength and the other including a second radiation including a second wavelength. Different or the same lithography tool may be used to generate the first and second radiation. For each die formed on the semiconductor device, a critical portion of the pattern is exposed using a first exposure operation that uses a first radiation with a first wavelength and a non-critical portion of the pattern is exposed using a second exposure operation utilizing the second radiation at a second wavelength. The resist material is chosen to be sensitive to both the first radiation having a first wavelength and the second radiation having the second wavelength.

Abstract: The present invention generally relates to methods of controlling UV lamp output to increase irradiance uniformity. The methods generally include determining a baseline irradiance within a chamber, determining the relative irradiance on a substrate corresponding to a first lamp and a second lamp, and determining correction or compensation factors based on the relative irradiances and the baseline irradiance. The lamps are then adjusted via closed loop control using the correction or compensation factors to individually adjust the lamps to the desired output. The lamps may optionally be adjusted to equal irradiances prior to adjusting the lamps to the desired output. The closed loop control ensures process uniformity from substrate to substrate. The irradiance measurement and the correction or compensation factors allow for adjustment of lamp set points due to chamber component degradation, chamber component replacement, or chamber cleaning.

Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

Abstract: A method for forming a germanium-enriched region in a heterojunction bipolar transistor and a heterojunction bipolar transistor comprising a germanium-enriched region. A base having a silicon-germanium portion is formed over a collector. Thermal oxidation of the base causes a germanium-enriched region to form on a surface of the silicon-germanium portion subjected to the thermal oxidation. An emitter is formed overlying the germanium-enriched portion region. The germanium-enriched region imparts advantageous operating properties to the heterojunction bipolar transistor, including improved high-frequency/high-speed operation.

Abstract: This invention disclosed a novel manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that an oxide-nitride-oxide (ONO) sandwich structure is employed instead of oxide-nitride dual layer structure before trench etching. Another aspect is, through the formation of silicon oxide spacer in trench sidewall and silicon oxide remaining in trench bottom in the deposition and etch back process, the new structure hard mask can effectively protect active region from impurity implanted in ion implantation process.

Abstract: Embodiments of the invention contemplate the formation of a high efficiency solar cell using novel methods to form the active doped region(s) and the metal contact structure of the solar cell device. In one embodiment, the methods include the steps of depositing a dielectric material that is used to define the boundaries of the active regions and/or contact structure of a solar cell device. Various techniques may be used to form the active regions of the solar cell and the metal contact structure.

Abstract: A method for forming a germanium-enriched region in a heterojunction bipolar transistor and a heterojunction bipolar transistor comprising a germanium-enriched region. A base having a silicon-germanium portion is formed over a collector. Thermal oxidation of the base causes a germanium-enriched region to form on a surface of the silicon-germanium portion subjected to the thermal oxidation. An emitter is formed overlying the germanium-enriched portion region. The germanium-enriched region imparts advantageous operating properties to the heterojunction bipolar transistor, including improved high-frequency/high-speed operation.

Abstract: Stability of an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer is critical for successful integration. UV-resistant diffusion barrier layers are formed by depositing the layer in a hydrogen-starved environment. Diffusion barrier layers can be made more resistant to UV radiation by thermal, plasma, or UV treatment during or after deposition. Lowering the modulus of the diffusion barrier layer can also improve the resistance to UV radiation.

Abstract: An imaging device comprising a plurality of photosensors, a shared diffusion region for receiving charge generated by the photosensors, and a dual conversion gain element that can be selectively coupled to the shared diffusion region to increase a conversion gain of the shared diffusion region. A method of operating such an imaging device is also described, comprising resetting a shared diffusion region, sampling a reset voltage level at the shared diffusion region, transferring charge accumulated in one of a plurality of photosensors to the shared diffusion region, sampling a pixel signal voltage level at the shared diffusion region, and activating a dual conversion gain element to increase a conversion gain of the shared diffusion region.

Abstract: Provided are methods of stabilizing an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer. Methods include modulating the optical properties reduces the effects of UV radiation on the dielectric diffusion barrier layer. The dielectric diffusion barrier can be made to absorb less UV radiation. A dielectric layer with UV absorbing properties may also be added on top of the diffusion barrier layer so less UV is transmitted. Both methods result in reduced interaction between UV radiation and the dielectric diffusion barrier.

Abstract: In a method of treating a semiconductor element which at least includes a semiconductor, a threshold voltage of the semiconductor element is changed by irradiating the semiconductor with light with a wavelength longer than an absorption edge wavelength of the semiconductor. The areal density of in-gap states in the semiconductor is 1013 cm?2eV?1 or less. The band gap may be 2 eV or greater. The semiconductor may include at least one selected from the group consisting of In, Ga, Zn and Sn. The semiconductor may be one selected from the group consisting of amorphous In—Ga—Zn—O (IGZO), amorphous In—Zn—O (IZO) and amorphous Zn—Sn—O (ZTO). The light irradiation may induce the threshold voltage shift in the semiconductor element, the shift being of the opposite sign to the threshold voltage shift caused by manufacturing process history, time-dependent change, electrical stress or thermal stress.

Abstract: A light-emitting device includes an n-type silicon thin film (2), a silicon thin film (3), and a p-type silicon thin film (4). The silicon thin film (3) is formed on the n-type silicon thin film (2) and the p-type silicon thin film (4) is formed on the silicon thin film (3). The n-type silicon thin film (2), the silicon thin film (3), and the p-type silicon thin film (4) form a pin junction. The n-type silicon thin film (2) includes a plurality of quantum dots (21) composed of n-type Si. The silicon thin film (3) includes a plurality of quantum dots (31) composed of p-type Si. The p-type silicon thin film (4) includes a plurality of quantum dots (41) composed of p-type Si. Electrons are injected from the n-type silicon thin film (2) side and holes are injected from the p-type silicon thin film (4) side, whereby light is emitted at a silicon nitride film (3).

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a base region and an emitter region in a front surface of a semiconductor layer. The method can include forming a first impurity implantation region by implanting first impurity of a first conductivity type into a back surface of the semiconductor layer. The method can include selectively forming a second impurity implantation region by selectively implanting second impurity of a second conductivity type into the first impurity implantation region. In addition, the method can include irradiating the first impurity implantation region and the second impurity implantation region with laser light. A peak of impurity concentration profile in a depth direction of at least one of the first impurity implantation region and the second impurity implantation region before irradiation with the laser light is adjusted to a depth of 0.05 ?m or more and 0.

Abstract: A method for forming a germanium-enriched region in a heterojunction bipolar transistor and a heterojunction bipolar transistor comprising a germanium-enriched region. A base having a silicon-germanium portion is formed over a collector. Thermal oxidation of the base causes a germanium-enriched region to form on a surface of the silicon-germanium portion subjected to the thermal oxidation. An emitter is formed overlying the germanium-enriched portion region. The germanium-enriched region imparts advantageous operating properties to the heterojunction bipolar transistor, including improved high-frequency/high-speed operation.

Abstract: A materials processing system comprises a thermal processing chamber including a heating source, a first noncontacting thermal measurement device positioned to measure temperature on a first area of the material being processed, and, a second noncontacting thermal measurement device positioned to measure temperature on a second area of the material being processed, the first device being relatively more sensitive to changes in surface emissivity than the second device. By comparing the outputs of the two devices, emissivity changes can be detected and used as a proxy for some physical change in the workpiece and thereby determine when the desired process has been completed. The system may be used to develop a process recipe, or it may be part of a system for real-time process control based on emissivity changes. Applicable processes include heating, annealing, dopant activation, silicide formation, carburization, nitridation, sintering, oxidation, vapor deposition, metallization, and plating.

Abstract: An improved method of producing solar cells utilizes a mask which is fixed relative to an ion beam in an ion implanter. The ion beam is directed through a plurality of apertures in the mask toward a substrate. The substrate is moved at different speeds such that the substrate is exposed to an ion dose rate when the substrate is moved at a first scan rate and to a second ion dose rate when the substrate is moved at a second scan rate. By modifying the scan rate, various dose rates may be implanted on the substrate at corresponding substrate locations. This allows ion implantation to be used to provide precise doping profiles advantageous for manufacturing solar cells.

Abstract: A method is described for monolithically forming a first memory level above a substrate, the method including: (a) forming a plurality of first substantially parallel, substantially coplanar conductors above the substrate, the first conductors extending in a first direction; (b) forming a plurality of vertically oriented contiguous p-i-n diodes above the first conductors, the contiguous p-in diode comprising semiconductor material crystallized in contact with a silicide, silicide-germanide, or germanide layer; (c) forming a plurality of second substantially parallel, substantially coplanar conductors, the second conductors above the contiguous p-i-n diodes, the second conductors extending in a second direction different from the first direction, each contiguous p-i-n diode vertically disposed between one of the first conductors and one of the second conductors; (d) and forming a plurality of dielectric rupture antifuses, each dielectric rupture antifuse disposed between one of the contiguous p-i-n diodes and

Abstract: A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective storage capacitor. The dual conversion gain element having a control gate switches in the capacitance of the capacitor to change the conversion gain of the floating diffusion region from a first conversion gain to a second conversion gain. In order to increase the efficient use of space, the dual conversion gain element gate also functions as the bottom plate of the capacitor. In one particular embodiment of the invention, a high dynamic range transistor is used in conjunction with a pixel cell having a capacitor-DCG gate combination; in another embodiment, adjacent pixels share pixel components, including the capacitor-DCG combination.

Abstract: To provide a low-cost high performance semiconductor device and a method for manufacturing the semiconductor device, a separate single-crystal semiconductor layer having a first region and a non-single-crystal semiconductor layer having a second region are provided over a substrate. Further, it is preferable that a cap film is formed over either the separate single-crystal semiconductor layer or the non-single-crystal semiconductor layer, and the first region and the second region are irradiated with a laser beam by applying the laser beam from above the cap film.