Abstract: A method of selectively removing silicon nitride is provided. The method includes: providing a wafer having silicon nitride on a surface of the wafer; supplying a mixture of phosphoric acid and a silicon-containing material into a process tank, in which the mixture has a predetermined silicon concentration; and submerging the wafer into the mixture within the process tank to remove the silicon nitride. An etching apparatus of selectively removing silicon nitride is also provided.

Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer.

Abstract: An ion implant apparatus and moveable ion beam current sensor are described. Various examples provide moving the ion beam current sensor during an ion implant process such that a distance between the ion beam current sensor and a substrate is maintained during scanning of the ion beam toward the substrate. The ion beam current sensor is disposed on a moveable support configured to move the ion beam current sensor in a first direction corresponding to the scanning of the ion beam while the substrate is moved in a second direction.

Abstract: Herein, an improved technique for processing a substrate is disclosed. In one particular exemplary embodiment, the technique may be realized with a system for processing one or more substrates. The system may comprise an ion source for generating ions of desired species, the ions generated from the ion source being directed toward the one or more substrates along an ion beam path; a substrate support for supporting the one or more substrates; a mask disposed between the ion source and the substrate support, the mask comprising a finger defining one or more apertures through which a portion of the ions traveling along the ion beam path pass; and a first detector for detecting ions, the first detector being fixedly positioned relative to the one or more substrates.

Abstract: A mechanism is provided by which delamination of a substrate of a system-in-package is prevented. A mold lock feature is provided within the substrate that allows the mold compound forming the encapsulant to flow into the mold lock feature, thereby anchoring the encapsulant to the substrate. The mold lock features can be provided in areas of the substrate where higher stresses due to component configuration are predicted. Aspects of the present invention provide for a method of forming the mold lock features that is compatible with current methods of forming laminate substrates, and thereby do not require an increase in cost for manufacturing the substrate.

Abstract: Provided is a flip-chip bonding apparatus (500) capable of stacking and bonding a second-layer of the semiconductor chip (30) onto a first-layer of the semiconductor chip (20) having first through-silicon vias, the second-layer of the semiconductor chip (30) having second through-silicon vias at positions corresponding to the first through-silicon vias.

Abstract: In some embodiments, a system includes (1) a controller configured to receive information regarding substrate uniformity; (2) a processing tool configured to perform a semiconductor device manufacturing process on a substrate; and (3) a laser delivery mechanism coupled to the controller, the laser delivery mechanism configured to selectively deliver laser energy to the substrate during processing within the processing tool so as to selectively heat the substrate during processing. The controller is configured to employ the substrate uniformity information to determine a temperature profile to apply to the substrate during processing within the processing tool and to employ the laser delivery mechanism to selectively heat the substrate during processing within the processing tool based on the temperature profile. Numerous other embodiments are provided.

Abstract: The present disclosure provides methods and systems for providing a similarity index in semiconductor process control. One of the methods disclosed herein is a method for semiconductor fabrication process control. The method includes steps of receiving a first semiconductor device wafer and receiving a second semiconductor device wafer. The method also includes a step of collecting metrology data from the first and second semiconductor device wafers. The metrology data includes a first set of vectors associated with the first semiconductor device wafer and a second set of vectors associated with the second semiconductor device wafer. The method includes determining a similarity index based in part on a similarity index value between a first vector from the first set of vectors and a second vector from the second set of vectors and continuing to process additional wafers under current parameters when the similarity index is above a threshold value.

Abstract: A manufacturing apparatus includes a chuck for contacting a peripheral portion of a workpiece. The apparatus includes a nozzle to eject a process fluid (liquid or gas) toward a first surface while the workpiece is in contact with the chuck. The apparatus also includes a plate having an opening configured such that a support fluid (liquid or gas) can be ejected toward a second surface of the workpiece while the workpiece is in contact with the chuck. In an example, the support fluid can be used to counteract a displacement of the interior portion in the direction perpendicular to the plane of the workpiece due to, for example, gravity and/or hydrostatic pressure of the process fluid.

Abstract: A laminate includes a surface on which a gate electrode is provided, and is made of a nitride semiconductor. The laminate includes a first layer having a first band gap, and a second layer provided between the first layer and the surface and having a second band gap which is larger than the first band gap. The first and second layers and form a joint surface by a hetero junction. The surface includes a surface defect density equal to or smaller than 1.7×106 cm?2.

Abstract: A bonding layer of the first wafer article is thermally treated and a bonding layer of a second wafer article is thermally treated in accordance with first and second process parameters, respectively prior to bonding the first wafer article with the second wafer article. First and second grid distortion in the first and second wafer articles is measured and a difference is determined between the first and second grid distortions. A prediction is made for maintaining the difference within a prescribed tolerance. At least one of the first process parameters and the second process parameters can be conditionally varied in accordance with the prediction. The thermally treating of the first wafer article and the thermally treating of the second wafer article can then be performed with respect to another pair of the first and second wafer articles prior to bonding the another pair of wafer articles to one another through their respective bonding layers.

Abstract: A semiconductor assembly includes a first substrate and a chip. The chip is coupled to and spaced apart from the substrate. Further, the chip has a first surface facing the substrate. The chip also has a warpage profile indicating stress imparted on the chip following a reflow operation. The assembly includes a back layer disposed on the chip on a second surface substantially opposite from the first surface. The back layer has a non-uniform thickness. Additionally, the thickness of the back layer on each of a plurality of elements of the chip is based on the warpage profile.

Abstract: A method and apparatus for a substrate support system for a substrate process chamber, the chamber comprising a chamber body enclosing a processing region, a primary substrate support and a secondary substrate support at least partially disposed in the processing region, the secondary substrate support circumscribing the primary substrate support, wherein one or both of the primary substrate support and the secondary substrate support are movable relative to each other, and the primary substrate support is rotatable relative to the secondary substrate support.

Abstract: LED dies are partially singulated while on an unthinned depth growth substrate. Slots are made through the streets separating the LED dies, but not through the growth substrate, leaving the now separated LED dies on the growth substrate. A secondary support is attached to the LED dies on the opposite surface from the growth substrate, and the growth substrate is thinned or removed, leaving the LED dies on the secondary support. Because the LED dies are separated while on the unthinned growth substrate, the likelihood of distortion before slicing is virtually eliminated, and the width of the streets between the LED dies may be correspondingly reduced.

Abstract: Processes for forming an actuator having a curved piezoelectric membrane are disclosed. The processes utilize a profile-transferring substrate having a curved surface surrounded by a planar surface to form the curved piezoelectric membrane. The piezoelectric material used for the piezoelectric actuator is deposited on at least the curved surface of the profile-transferring substrate before the profile-transferring substrate is removed from the underside of the curved piezoelectric membrane. The resulting curved piezoelectric membrane includes grain structures that are columnar and aligned, and all or substantially all of the columnar grains are locally perpendicular to the curved surface of the piezoelectric membrane.

Abstract: Substrate processing systems and methods are described for processing substrates having two or more regions. The processing includes one or more of molecular self-assembly and combinatorial processing. At least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one region of the substrate relative to at least one other region of the substrate. Processing systems are described that include numerous processing modules. The modules include a site-isolated reactor (SIR) configured for one or more of molecular self-assembly and combinatorial processing of a substrate.

Abstract: In a method for removing metal at the edge of a wafer, including from a notch in the edge of the wafer, water is dripped or otherwise supplied onto the up-facing metal-plated front side of the wafer, while rotating the wafer. A metal etchant, such as sulfuric acid, is provided onto the back side of the wafer, at a flow rate multiple times greater than the water flow rate. The etchant flows over the edge of the wafer and the notch, and onto an annular edge on the front side of the wafer. The metal plated in the notch is removed, even if the notch has a radial depth greater than the width of the exclusion zone. The flow rates of the water and the etchant, and the rotation speed may be adjusted to provide a static water film, with the etchant diffusing into the outer edge of the water film.

Abstract: Implementations of the present disclosure generally relate to methods and apparatus for forming a film on a substrate. More particularly, implementations of the present disclosure relate to methods and apparatus for heteroepitaxial growth of crystalline films. In one implementation, a method of heteroepitaxial deposition of a strain relaxed buffer (SRB) layer on a substrate is provided. The method comprises epitaxially depositing a buffer layer over a dissimilar substrate, rapidly heating the buffer layer to relax the buffer layer, rapidly cooling the buffer layer and determining whether the buffer layer has achieved a desired thickness.

Abstract: A method of controlling a threshold voltage is provided. The method of controlling a threshold voltage includes performing a film-thickness measuring step to measure the thickness of a film layer on a wafer to obtain a film-thickness value. Then, at least one parameter is decided, selected, or generated according to the film-thickness value. Next, an ion implantation process is performed on the wafer, wherein the ion implantation process is executed according to the parameter to form a threshold voltage adjustment region in the wafer below the film layer.

Abstract: Thermal processing and alignment methods and processes used during fabrication of semiconductor devices are provided. One method includes, for instance: obtaining a device after at least one laser annealing process is completed, the device including a substrate surface and at least one layer over the substrate surface; applying a mask layer to the at least one layer; performing lithography on the mask layer to form a top layer; positioning a first contact-to-gate layer over the top layer; checking alignment of electrical connections between the substrate surface and the first contact-to-gate layer; and determining if an adjustment is needed to at least one parameter of at least one laser annealing beam used during the laser annealing process. In enhanced aspects, the at least one laser annealing process includes: performing three laser anneals; applying three mask layers; and performing lithography three times.

Abstract: A method of forming a forming a semiconductor device comprises forming at least one semiconductor device structure over a surface of a wafer. An opposing surface of the wafer is subjected to at least one chemical-mechanical polishing process to form a modified opposing surface of the wafer comprising at least one recessed region and at least one elevated region. Additional methods of forming a semiconductor device, and methods of reducing stress on a wafer are also described.

Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract: There is provided an inspection method for inspecting a substrate supporting portion configured to support a substrate during an exposure performed by an exposure apparatus, the method including: irradiating a surface of the exposed substrate with an illumination light beam; detecting reflected light from a pattern in the irradiated surface; determining a focusing state at the time of exposing the pattern of the substrate based on the detected reflected light; and inspecting a state of the substrate supporting portion based on the focusing state.

Abstract: A method of monitoring an OLED production process for making a production process OLED device, the production process OLED device having a layered structure comprising an anode layer and a cathode layer, said anode and cathode layers sandwiching a hole injection layer, a hole transport layer and at least one organic light emitting layer, the method comprising: fabricating at least one similar OLED device to said production process OLED device, wherein said at least one similar OLED device has a layered structure corresponding to said production process OLED device and a range of hole injection and/or transport layer thicknesses; characterising a spectral variation of a light output of said at least one similar OLED device with respect to variation in said hole injection and/or transport layer thickness; partially fabricating a said production process OLED device using said production process, wherein said partial fabrication comprises depositing one or more layers comprising at least said hole injection and/o

Abstract: This disclosure describes systems, methods, and apparatus for reducing a DC bias on a substrate surface in a plasma processing chamber due to cross coupling of RF power to an electrode coupled to the substrate. This is brought about via tuning of a resonant circuit coupled between the substrate and ground based on indirect measurements of harmonics of the RF field level at a surface of the substrate. The resulting reduction in DC bias allows a lower ion energy than possible without this resonant circuit and tuning thereof.

Abstract: The invention is directed towards methods and compositions for identifying the amount of ammonium acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of ammonium acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of ammonium acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the ammonium acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first group identifier allocated to a first group of semiconductor wafers is detected. The first group of semiconductor wafers includes a first semiconductor wafer to be processed first among the first group. A first processor of a plurality of processors, which process respective ones of the first group of semiconductor wafers, are determined based on the first group identifier. The first processor is used for processing the first semiconductor wafer. The first semiconductor wafer is supplied to the first processor.

Abstract: Target pattern layouts that include lower and upper target patterns are designed. Each lower target pattern is combined with a upper target pattern that at least partially overlaps a top surface thereof to form combination structures. The combination structures are divided into first and second combination structures. A first target pattern is formed from the lower target pattern in the first combination structure and a third target pattern is formed from the upper target pattern in the first combination structure. The first and third target patterns are formed in first and third lithography processes, respectively. A second target pattern is formed from the lower target pattern in the second combination structure and a fourth target pattern is formed from the upper target pattern in the second combination structure. The second and fourth target patterns are formed in second and fourth lithography processes, respectively.

Abstract: An analysis device includes an X-ray generation part configured to generate four monochromatic X-rays with different energies to irradiate a sample, an electrically conductive sample stage configured to place the sample thereon and formed of an electrically conductive material, an electrode configured to detect an electric current carried by irradiating the sample with the four monochromatic X-rays with different energies, and an electric power source configured to apply a voltage between the electrically conductive sample stage and the electrode, wherein the four monochromatic X-rays with different energies are X-rays included within a range from an absorption edge of a compound semiconductor included in the sample to a higher energy side of 300 eV.

Abstract: A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes a conductive layer. The conductive layer includes conductive tracks which may be defined by photomasks. The conductive tracks may have quality characteristics. Distinct quality characteristics of distinct conductive tracks may be compared. Based on the comparison, signals and supply voltage may be routed on particular conductive tracks.

Abstract: Methods and apparatus for gas delivery are disclosed herein. In some embodiments, a gas delivery system includes an ampoule for storing a precursor in solid or liquid form, a first conduit coupled to the ampoule and having a first end coupled to a first gas source to draw a vapor of the precursor from the ampoule into the first conduit, a second conduit coupled to the first conduit at a first junction located downstream of the ampoule and having a first end coupled to a second gas source and a second end coupled to a process chamber, and a heat source configured to heat the ampoule and at least a first portion of the first conduit from the ampoule to the second conduit and to heat only a second portion of the second conduit, wherein the second portion of the second conduit includes the first junction.

Abstract: A dispensing apparatus includes a dispensing unit having a main body, a channel through the main body, and a plurality of nozzles connected to the main body, the plurality of nozzles being configured to dispense fluid flowing in the channel, a gap sensor unit configured to determine size of gaps between adjacent nozzles in the dispensing unit, and a thermal expansion adjusting unit configured to thermally expand or contract the main body of the dispensing unit to adjust the gap size between adjacent nozzles to a predetermined size, based on the gap size determined by the gap sensor unit.

Abstract: A method of manufacturing a semiconductor device according to one embodiment includes: preparing a semiconductor water which is partitioned into a plurality of first semiconductor chips, the plurality of first semiconductor chips including a first group of first semiconductor chips and a second group of first semiconductor chips; providing a second semiconductor chip over at least one of first semiconductor chips of the first group; providing a sealer on the first semiconductor chips of the second group; and grinding one face of the semiconductor wafer which is on the opposite side from a face on which the second semiconductor chip and the sealer are provided.

Abstract: A replacement metal gate transistor and methods of forming replacement metal gate transistors are described. Various examples provide methods of manufacturing a replacement metal gate transistor that includes depositing a dielectric layer into a trench, wherein the dielectric layer is deposited onto the bottom of the trench and the sidewalls of the trench, depositing a first metal layer into the trench, wherein the first metal layer is deposited onto the bottom of the trench and the sidewalls of the trench over the dielectric layer, depositing a second metal layer into the trench, wherein the second metal layer is deposited onto the bottom of the trench and the sidewalls of the trench over the first metal layer, removing at least a portion of the second metal layer from the sidewalls of the trench, and depositing a conducting layer into the trench. Other embodiments are disclosed and claimed.

Abstract: A bonding apparatus for 3D integration may include a plurality of infrared microscopes that emit and receive infrared light for imaging, a first bonding chuck that holds a first semiconductor structure, and a second bonding chuck that holds a second semiconductor structure, whereby the second bonding chuck has a plurality of openings that are transparent to the received infrared light. A force pin is coupled to the first bonding chuck for applying a predetermined force to the first semiconductor structure for bonding to the second semiconductor structure. A temperature controller is coupled to the second bonding chuck, whereby the temperature controller applies a predetermined temperature to the second semiconductor structure, such that, prior to the bonding, the first and the second semiconductor structure are de-aligned with respect to each other using the plurality of infrared microscopes and the plurality of openings.

Abstract: An evaporation apparatus comprises a chamber configured to contain at least one dispensing nozzle and at least one substrate to be coated. The chamber has at least one adjustable shielding member defining an adjustable aperture. The member is positioned between the at least one dispensing nozzle and the at least one substrate. The aperture is adjustable in at least one of the group consisting of area and shape. The at least one adjustable shielding member has a heater.

Abstract: A system for and method of processing an article such as a semiconductor wafer is disclosed. The wafer includes first and second surfaces which are segmented into a plurality of first and second zones. The first surface of the wafer, for example, on which devices or ICs are formed is processed by, for example, laser annealing while the second surface is heated with a backside heating source. Corresponding, or at least substantially corresponding, zones on the first and second surfaces are processed synchronously to reduce variations of post laser anneal thermal budget across the wafer.

Abstract: A substrate treating apparatus including: a chamber capable of accommodating a substrate; a treating part which conducts a predetermined treatment associated with forming a coating film containing a metal to the substrate accommodated in the chamber; and a detection part which detects a concentration of a predetermined gas containing a chalcogen element within a gas inside the chamber.

Abstract: A method for wafer bonding includes measuring grid distortion for a mated pairing of wafers to be bonded to determine if misalignment exists between the wafers. During processing of subsequent wafers, magnification of one or more lithographic patterns is adjusted to account for the misalignment. The subsequent wafers are bonded with reduced misalignment.

Abstract: Thermal processing and alignment methods and processes used during fabrication of semiconductor devices are provided. One method includes, for instance: obtaining a device after at least one laser annealing process is completed, the device including a substrate surface and at least one layer over the substrate surface; applying a mask layer to the at least one layer; performing lithography on the mask layer to form a top layer; positioning a first contact-to-gate layer over the top layer; checking alignment of electrical connections between the substrate surface and the first contact-to-gate layer; and determining if an adjustment is needed to at least one parameter of at least one laser annealing beam used during the laser annealing process. In enhanced aspects, the at least one laser annealing process includes: performing three laser anneals; applying three mask layers; and performing lithography three times.

Abstract: Methods and processes for establishing a rework threshold for layers applied after thermal processing during fabrication of semiconductor devices are provided. One method includes, for instance: obtaining a device after at least one laser annealing process is completed, the device including a substrate surface and at least one layer over the substrate surface; performing lithography on the at least one layer; positioning a first contact-to-gate layer over the at least one layer; checking alignment of electrical connections between the substrate surface and the first contact-to-gate layer; determining if an overlay error is present; and adjusting at least one subsequent fabrication process pursuant to the overlay error.

Abstract: A method for wafer bonding includes measuring grid distortion for a mated pairing of wafers to be bonded to determine if misalignment exists between the wafers. During processing of subsequent wafers, magnification of one or more lithographic patterns is adjusted to account for the misalignment. The subsequent wafers are bonded with reduced misalignment.

Abstract: The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD).

Abstract: A system and method of applying power to a target plasma chamber include, characterizing a no plasma performance slope of the target plasma chamber, applying a selected plasma recipe to a first wafer in the target chamber, the selected plasma recipe includes a selected power set point value and monitoring a recipe factor value on the RF electrode. A ratio of process efficiency is generated comparing the reference chamber and the target chamber, the generating using as inputs the no plasma performance slopes of the target chamber and the reference chamber and the monitored recipe factor value. An adjusted power set point value is calculated, the adjusted power set point configured to cause power delivered to a plasma formed in the target chamber to match power that would be delivered to a reference plasma formed in the reference chamber.

Abstract: A plasma processing method in which a stable process region can be ensured in a wide range, from low microwave power to high microwave power. The plasma processing method includes making production of plasma easy in a region in which production of plasma by continuous discharge is difficult, and plasma-processing an object to be processed, with the generated plasma, wherein the plasma is produced by pulsed discharge in which ON and OFF are repeated, radio-frequency power for producing the pulsed discharge, during an ON period, is a power to facilitate production of plasma by continuous discharge, and a duty ratio of the pulsed discharge is controlled so that an average power of the radio-frequency power per cycle is power in the region in which production of plasma by continuous discharge is difficult.

Abstract: A semiconductor device manufacturing method includes sealing a first surface of a semiconductor wafer with a resin, causing a resin-made warp suppression member to be adhered to a second surface on the opposite side of the first surface of the semiconductor wafer and causing the warp suppression member to shrink, measuring the amount of warp of the semiconductor wafer, and forming cuts in the warp suppression member in accordance with the amount of warp of the semiconductor wafer.

Abstract: A method for manufacturing microelectromechanical flexural resonators with a deforming element that has an elongate body extending along a spring axis. A deforming element is positioned on the semiconductor wafer with a defined nominal n-type doping concentration such that a crystal orientation angle is formed between the spring axis of the deforming element and a crystal axis of the silicon semiconductor wafer. The combination of the crystal orientation angle and the nominal n-type doping concentration is adjusted to a specific range, based on total frequency error of the deforming element in a broad temperature range. The combination is optimized to a range where also sensitivity to variations in the material properties is minimized.

Abstract: A system and method for determining the edge or region where a saw first enters a silicon brick, and using this information to process this region differently is disclosed. This region, referred to as the saw entry region, may be thinner, or have a rougher texture than the rest of the substrate. This difference may impact the substrate's ultimate performance. For example, if the substrate is processed as a solar cell, the performance of the saw entry region may be suboptimal.

Abstract: A deposition amount measuring apparatus includes a plate-shaped body having a rotating shaft, a plurality of deposition amount sensors along side surfaces of the body, the deposition amount sensors being configured to measure an amount of deposition material, and a housing surrounding the body, the housing including an inflow port that exposes one of the deposition amount sensors.