Abstract: The present invention provides a method for producing a semiconductor substrate which comprises the steps of growing a first semiconductor layer on a substrate in liquid phase at a properly controlled temperature for eliminating defects and growing a second semiconductor layer on the first semiconductor layer in liquid phase at a higher temperature; a solar cell produced by a method comprising a step of anodizing the surface of the first and second layer side of the semiconductor substrate produced by the liquid-phase growth method; a liquid-phase growth apparatus comprising means for storing a melt, means for changing the temperature of the stored melt, and means for bringing an oxygen-containing substrate into contact with the melt, wherein a substrate is brought into contact with the melt at a temperature so as to suppress the stacking faults contained in the semiconductor layer grown on the surface of the substrate.

Abstract: A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) is formed over a semiconductor region (e.g., a silicon substrate). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench can be etched in the semiconductor region. The trench would be substantially aligned to the second material.

Abstract: A process for producing a crystalline thin film is provided which comprises melting and resolidifying a starting thin film having regions different in the state coexisting continuously. A small region of the starting thin film has a size distribution of number concentration of crystal grains or crystalline clusters different from that of the surrounding region. In the process of melting and resolidification, the crystal grain grows preferentially in the one region to control the location of the crystal grain in the crystalline thin film.

Abstract: A method of fabricating a semiconductor structure including the steps of providing a silicon substrate (10) having a surface (12), forming on the surface (12) of the silicon substrate (10), by atomic layer deposition (ALD), a monocrystalline seed layer (20;21′) comprising a silicate material and forming, by atomic layer deposition (ALD) one or more layers of a monocrystalline high dielectric constant oxide (42) on the seed layer (20;21′).

Abstract: Performance of the high resistance resistor, which is polysilicon, is improved by treating the surface of the polysilicon layer in mixed signal integrated circuits for ADSL (Asymmetric Digital Subscriber Line) broadband service application. This treated surface of the polysilicon layer will prevent ions in the resistor from out-diffusion when performing an annealing step after forming the resistor.

Abstract: In order to make possible formation of a deposited film of a relatively large area at a treatment rate which could not accomplished by the plasma process of the prior art, and in order to make possible stable production of the deposited film without variation in film quality, in an apparatus and a method for forming a deposited film, a part of a reaction vessel is formed of a dielectric member, at least one high-frequency electrode is arranged so as to face at least one substrate with interposition of the dielectric member, an earth shield is arranged so as to cover the reaction vessel and the high-frequency electrode, plasma is generated between the high-frequency electrode and the substrate, and a deposited film is formed under the conditions in which the following equation: 0.

Abstract: In a process for mitigating and/or eliminating the abnormal growth of underlying polysilicon in dichloro silane-based CVD polycide WSix films, a first technique conducts the deposition of the underlying polysilicon layer at a temperature that substantially avoids crystallization of the underlying polysilicon. A second approach reduces the exposure (for example time period and or concentration) of the mono-silane SiH4 post flush, so as to avoid infusion of silicon into the underlying polysilicon layer, and resulting abnormal growth. In this manner, abnormal effects, such as stress fractures formed in subsequent layers, can be eliminated.

Abstract: A process for forming a thin layer exhibiting a substantially uniform property on an active surface of a semiconductor substrate. The process includes varying the temperature within a reaction chamber while a layer of a material is formed upon the semiconductor substrate. Varying the temperature within the reaction chamber facilitates temperature uniformity across the semiconductor wafer. As a result, a layer forming reaction occurs at a substantially consistent rate over the entire active surface of the semiconductor substrate. The process may also include oscillating the temperature within the reaction chamber while a layer of a material is being formed upon a semiconductor substrate.

Abstract: An improved method of trench isolation formation includes, for one embodiment, applying a polysilicon layer above a planarized trench, and converting the polysilicon to oxide prior to etching the active areas. This converted oxide is denser than the materials usually used to fill the trench, such as TEOS, and results in less over-etching of the trench isolation region. The quality of the dielectric isolation is consequently improved, and in particular, less leakage current flows across the trench isolation region. Moreover, less leakage current flows from a subsequently formed local interconnect layer.

Abstract: A method and apparatus for forming a dielectric layer. A dielectric precursor solution is deposited onto a surface of a substrate. The substrate is spun to spread the dielectric precursor solution over the surface of the substrate. A catalyst is introduced through a filter, wherein the filter causes a substantially homogenous distribution of the catalyst within the substrate, wherein a dielectric layer forms containing pores and wherein a solvent is contained in the pores. The solution is dried to form the dielectric layer using a carrier gas after introducing the catalyst, wherein the carrier gas places a positive pressure within the pores while removing the solvent to form a low-k dielectric layer.

Abstract: A multilayered wafer with a thick sacrificial layer, which is obtained by forming a sacrificial layer of oxidized porous silicon or porous silicon and growing an epitaxial polysilicon layer on the sacrificial layer, and a fabrication method thereof are provided. The multilayered wafer with a thick sacrificial layer adopts a porous silicon layer or an oxidized porous silicon layer as a sacrificial layer such that a sufficient gap can be obtained between a substrate and a suspension structure upon the manufacture of the suspension structure of a semiconductor actuator or a semiconductor inertia sensor. Also, in a fabrication method of the wafer according to the present invention, a p+-type or n+-type wafer doped at a high concentration is prepared for, and then a thick porous silicon layer can be obtained simply by anodic-bonding the surface of the wafer. Also, when polysilicon is grown on a porous silicon layer by an epitaxial process, it is grown faster than when single crystal silicon is grown.

Abstract: A method for planarizing a polysilicon layer is described. A polysilicon layer is etched with an oxygen-based gas and a halogen-based gas. The oxygen-based gas comprises an nitrogen oxide oxygen gas. The nitrogen oxide gas includes NO, NO2, N2O, or the combination thereof. The halogen-based gas includes a F, Cl, Br., I, NF3, SF6, Cl2, HCl, SiCl4, fluorocarbon, or a combination thereof. The fluorocarbon includes CF4, CHF3, CH2F2, CH3F, or the like.

Abstract: A method of coating an amorphous silicon layer. An amorphous silicon layer is directly deposited on the polysilicon nodes by a self-aligned method. A chemical mechanical polishing process is performed to control the thickness of the amorphous silicon layer. No additional photoresist is used during the whole processes. Therefore, the duration for deposition can be reduced and the quality of the amorphous silicon film is improved.

Abstract: A method for forming a layer of hemispherical silicon grains having a desired density and a desired shape in order to increase the surface area of the storage electrode of a capacitor. The method involves the formation of a thin oxide film over an under silicon layer to be formed with hemispherical silicon grains, so that the formation of those hemispherical silicon grains can be carried out in such a manner that the hemispherical silicon grains have a desired density and a desired shape under given conditions irrespective of whether or not the under silicon layer is doped with impurity ions and the crystalline structure of the under silicon layer.

Abstract: A method is described for cleaning a silicon surface of a semiconductor wafer in a vacuum chamber while radiantly heating said silicon surface to maintain it within a first temperature range in the presence of hydrogen gas; then quickly cooling the wafer down to a second temperature range by reducing the radiant heat; and then forming a layer of either polysilicon or oxide over the cleaned surface within this second temperature range without removing the cleaned wafer from the chamber. By cleaning the wafer and then depositing polysilicon or growing oxide over the cleaned silicon surface in the same vacuum chamber, formation of oxides and other contaminants on the cleaned silicon surface between the cleaning step and the deposition or growth step is inhibited, resulting in a higher quality polysilicon or oxide layer formed over the cleaned silicon surface.

Abstract: A process for fabricating a semiconductor device comprising the steps of: introducing into an amorphous silicon film, a metallic element which accelerates the crystallization of the amorphous silicon film; applying heat treatment to the amorphous silicon film to obtain a crystalline silicon film; irradiating a laser beam or an intense light to the crystalline silicon film; and heat treating the crystalline silicon film irradiated with a laser beam or an intense light.

Abstract: Catalytic elements such as Ni are intentionally combined with defects that remain inside of a semiconductor substrate or thin film so that the energy state of the defects comes to a stable state. In this state, a heat treatment is conducted in an atmosphere containing halogen element or XV element, and gettering is conducted in such a manner that the catalytic element is taken in an oxide film. The bonds which are divided by separating the catalytic element are recombined through a heat treatment, thereby being capable of improving crystalline property of the semiconductor substrate or thin film remarkably.

Abstract: An adherent and metallurgically stable metallization system for diamond is presented. The big improvement in metallurgical stability is attributed to the use of a ternary, amorphous Ti--Si--N diffusion barrier. No diffusion between the layers and no delamination of the metallization was observed after annealing the schemes at 400.degree. C. for 100 hours and at 900.degree. C. for 30 minutes. Thermal cycling experiments in air from -65 to 155.degree. C. and adhesion tests were performed. Various embodiments are disclosed.

Abstract: A method for forming field oxide comprises the steps of forming a pad oxide layer over a semiconductor substrate, then forming a silicon layer over the pad oxide layer. A patterned mask is formed over the silicon layer and the silicon layer is etched to form openings in the silicon layer. Next, a blanket nitride layer is formed over the silicon and within the openings, and the nitride layer is then planarized to remove the nitride which overlies the silicon which leaves the nitride in the openings. Subsequent to the step of planarizing the nitride, the silicon layer is removed thereby forming openings in the nitride layer. The substrate is oxidized at the openings in the nitride layer to form field oxide from the substrate.

Abstract: An integrated circuit transistor is provided having a gate oxide and a gate conductor arranged upon a semiconductor topography, the gate oxide and gate conductor are formed within a common chamber. The initial semiconductor topography includes a silicon substrate having isolation regions disposed within its upper surface. The semiconductor topography may include an defined region, or well, doped opposite the substrate. The semiconductor topography is first placed in the common chamber. A separate chamber is operably placed gaseous communication with the common chamber. A plasma is created within the separate chamber, causing nitrogen, silicon, and oxygen containing compounds therein to form ions, molecular fragments, and excited molecules which are transported to the common chamber. The ions, molecular fragments, and excited molecules react and bombard the surface of the semiconductor topography to form an oxide layer thereon. The oxide layer is incorporated with nitrogen atoms which act as barrier atoms.

Abstract: The invention provides an evaluation method for a polycrystalline silicon film by which the film quality of a polycrystalline silicon film can be evaluated by a simple method. A silicon oxide film is formed on a p-type silicon substrate, and a photo-resist film having two openings therein is formed on the silicon oxide film. The silicon oxide film is etched to form openings therein, and a polycrystalline silicon film is deposited. Then, arsenic is ion implanted, and heat treatment is performed to form a diffused layer. The polycrystalline silicon film is patterned to form polycrystalline silicon electrodes. A voltage is applied between the polycrystalline silicon electrodes to measure a withstanding voltage and a condition of the diffused layer is recognized, and evaluation of the film quality of the polycrystalline silicon film and an interface condition between the polycrystalline silicon film and the p-type silicon substrate is performed based on the recognition.

Abstract: Concentration of metal element which promotes crystallization of silicon and which exists within a crystal silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is implemented after introducing nickel element to an amorphous silicon film 103. Then, after obtaining the crystal silicon film, another heat treatment is implemented within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. At this time, HCl or the like is added to the atmosphere. A thermal oxide film 106 is formed in this step. At this time, gettering of the nickel element into the thermal oxide film 106 takes place. Next, the thermal oxide film 106 is removed. Thereby, a crystal silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.

Abstract: A silicon structure is formed that includes a free-standing wall having opposing roughened inner and outer surfaces using ion implantation and an unimplanted silicon etching process which is selective to implanted silicon. In general, the method provides a recess in a layer of insulating material into which a polysilicon layer is formed. A layer of HSG or CSG polysilicon is subsequently formed on the polysilicon layer, after which ions are implanted into both the layer of HSG or CSG polysilicon and the underlying polysilicon layer. The aforementioned selective etching process is then conducted to result in a relatively unimplanted portion being etched away and a highly implanted portion being left standing to form the free-standing wall. The free-standing wall has an inner surface that is roughened by the layer of HSG or CSG polysilicon. The free-standing wall also has a roughened outer surface to which has been transferred a near-impression image topography of the opposing inner surface.

Abstract: A process for fabricating bottom electrodes for storage capacitors of memory cell units of a DRAM is disclosed. The process employs the use of a protective dielectric layer that serves as an etching shield in the process of fabrication of the capacitor electrode. The HSG-Si layer that substantially increases the surface area of the capacitor electrode can be protected from etching damage, thereby avoiding short-circuiting phenomena found in the conventional fabrication processes. Improved data retention time capability of the DRAM memory cells can thus be obtained utilizing the fabrication process of the invention.

Abstract: Alternate formation of high-resistance and low-resistance layers form a thin film with reduced dopant gradient in its thickness. A desired sheet resistance is attained by adjusting the thickness of the stacked layers, the degree of doping of the film, and the number of layers used to make the thin film during the film formation process.

Abstract: A number of wafers are loaded into a reaction vessel on a wafer boat; monosilane gas, phosphine gas and N.sub.2 O gas are supplied to form amorphous silicon film doped with, e.g., phosphorus; and then the wafers are annealed in, e.g., a different reaction tube to polycrystallize the amorphous silicon film. Os (Oxygen) generated by decomposition of N.sub.2 O are taken into the film. The Os become nuclei of the silicon crystals, and the crystals become fine and have size uniformity. As a result, high uniformity of resistance values of micronized devices of the polysilicon film can be obtained. Resistance values of the polysilicon film can be easily controlled by addition of oxygen. As a result, high uniformity of resistance values of micronized devices of the polysilicon film can be obtained.

Abstract: A method and apparatus of forming local interconnects in a MOS process deposits a layer of polysilicon over an entire region after several conventional MOS processing steps. The region is then masked to provide protected regions and unprotected regions. The mask may be used to define local interconnects and other conductive elements such as the source and drain contact regions for a MOS transistor. After masking, the region is bombarded with atoms to enhance the oxidation potential of the unprotected regions. The masking is removed and the substrate is then exposed to oxidizing conditions which cause the unprotected regions to rapidly oxidize to form a thick oxide layer. The formerly protected polysilicon regions may then be doped to render them conductive.

Abstract: A fabrication process for rendering, for example, amorphous silicon (a-Si) films into polycrystalline silicon (poly-Si) films initially commences with the deposition of the a-Si film on a substrate such as glass. The a-Si film is then exposed to a particle flux (e.g. a plasma or a neutral beam). The resulting treatment apparently causes an action that enhances a subsequent crystallization process. The treatment occurs at a temperature well below any level which causes a change in the substrate. The particle flux treatment is followed by an anneal step that enables a rapid crystallization. By appropriate masking prior to the treatment, crystallization in non-treated areas is prevented while crystallization in treated areas occurs during the anneal procedure.