Melt-back Patents (Class 438/955)
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Patent number: 8420496Abstract: A PIN diode has an n? drift layer, a p anode layer, an n buffer layer, an n+ layer, a front surface electrode and a back surface electrode. The n+ layer has an impurity concentration having a stepwise profile substantially fixed for a predetermined depth measured from a second major surface. The n buffer layer has an impurity concentration gently decreasing as seen at the n+ layer toward n? drift layer. The n? drift layer has an impurity concentration reflecting that of the semiconductor substrate and thus substantially fixed depthwise. The p anode layer has an impurity concentration relatively steeply decreasing as seen at a first major surface toward the n? drift layer. Thus there can be provided a semiconductor device that can provide characteristics, as desired, with high precision to accommodate the product applied, and a method of fabricating the semiconductor device.Type: GrantFiled: August 19, 2010Date of Patent: April 16, 2013Assignee: Mitsubishi Electric CorporationInventor: Hidenori Fujii
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Patent number: 7115503Abstract: A method and apparatus for processing a thin metal layer on a substrate to control the grain size, grain shape, and grain boundary location and orientation in the metal layer by irradiating the metal layer with a first excimer laser pulse having an intensity pattern defined by a mask to have shadow regions and beamlets. Each region of the metal layer overlapped by a beamlet is melted throughout its entire thickness, and each region of the metal layer overlapped by a shadow region remains at least partially unmelted. Each at least partially unmelted region adjoins adjacent melted regions. After irradiation by the first excimer laser pulse, the melted regions of the metal layer are pemitted to resolidify. During resolidification, the at least partially unmelted regions seed growth of grains in adjoining melted regions to produce larger grains.Type: GrantFiled: October 9, 2001Date of Patent: October 3, 2006Assignee: The Trustees of Columbia University in the City of New YorkInventor: James S. Im
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Patent number: 6869863Abstract: Metal-grade silicon is melted and solidified in a mold to form a plate-shaped silicon layer and a crystalline silicon layer is made thereon, thereby providing a cheap solar cell without a need for a slicing step.Type: GrantFiled: March 3, 2003Date of Patent: March 22, 2005Assignee: Canon Kabushiki KaishaInventor: Shoji Nishida
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Patent number: 6809015Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1-60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 &mgr;m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.Type: GrantFiled: January 9, 2003Date of Patent: October 26, 2004Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Shoji Akiyama, Yuuichi Matsumoto, Masaro Tamatsuka
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Patent number: 6387780Abstract: Metal-grade silicon is melted and solidified in a mold to form a plate-shaped silicon layer and a crystalline silicon layer is made thereon, thereby providing a cheap solar cell without a need for a slicing step.Type: GrantFiled: September 18, 1997Date of Patent: May 14, 2002Assignee: Canon Kabushiki KaishaInventor: Shoji Nishida
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Patent number: 5821134Abstract: Disclosed is a method of producing an electron-absorption modulator having a reverse mesa structure. In the electron-absorption modulator, a first clad of a first conductivity type, an active layer of the first conductivity type, a second clad layer of a second conductivity type and an ohmic contact layer of the second conductivity type are formed on a semiconductor substrate of the first conductivity type. Then, a predetermined mask pattern is formed on the ohmic contact layer. Afterwards, the ohmic contact layer is etched by using the mask pattern. Then, the second clad layer and the active layer below the ohmic contact layer are etched in the form of the reverse mesa structure to expose the first clad layer. Then, the first clad layer is etched at a predetermined depth in the form of a mesa structure.Type: GrantFiled: June 25, 1997Date of Patent: October 13, 1998Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Byung-Kwon Kang, Jung-Koo Kang, You-Ri Jo, Jong-Deog Kim, Seung-Jo Jeong, Young-kun Sin
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Patent number: 5786234Abstract: A method of fabricating a semiconductor laser includes successively epitaxially growing on a first conductivity type semiconductor substrate, a first conductivity type lower cladding layer, an active layer, a second conductivity type first upper cladding layer having a relatively high etching rate in an etchant, a second conductivity type etch stopping layer having a relatively low etching rate in the etchant, a second conductivity type second upper cladding layer, and a second conductivity type first contact layer; forming a stripe-shaped mask on the first contact layer; removing portions of the first contact layer and the second upper cladding layer in a first wet etching step to expose the etch stopping layer; removing portions of the second upper cladding layer in a second wet etching step to form a stripe-shaped ridge structure having a reverse mesa cross section without an intermediate construction; growing a first conductivity type current blocking layer contacting both sides of the ridge structure; anType: GrantFiled: June 12, 1997Date of Patent: July 28, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yutaka Nagai, Hitoshi Tada