Abstract: Semiconductor structure and method for fabricating a semiconductor structure are provided. A substrate including device regions and an isolation region located adjacent to and between the device regions is provided. A fin on the substrate, gate structures across the fin at the device regions, source/drain doped regions in the fin at two sides of each of the gate structures, and a sacrificial gate across the fin at the isolation region are provided. The sacrificial gate and a portion of the fin near a bottom of the sacrificial gate are removed, thus forming a first opening in the fin. An insulation structure in the first opening is formed. Two sides of the sacrificial gate are in contact with the source/drain doped regions at adjacent device regions. A top surface of the insulation structure is flush with or higher than top surfaces of the source/drain doped regions.

Abstract: The instant disclosure discloses a method comprises receiving a substrate having a first region and a second region defined thereon and an insulating structure formed there-between; forming, extending across the first region and the second region, a gate stack including a dielectric layer and a gate poly layer formed thereon; forming a first well mask covering the second region while defining a first opening that projectively overlaps the first region to partially exposes the gate poly layer; performing a first doping process, through the first opening and the gate stack, to form a first well in the substrate beneath the first opening; and performing a second doping process through the first opening to form a first gate conductor in the gate poly layer.

Abstract: To provide a composition for removing photoresist residue and/or polymer residue formed in a process for producing a semiconductor circuit element, and a removal method employing same. A composition for removing photoresist residue and/or polymer residue, the composition containing saccharin and water, and the pH being no greater than 9.7.

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.

Abstract: A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin.

Abstract: An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.

Abstract: A method of forming a semiconductor structure includes the following steps. At least a first source/drain region and a second source/drain region are formed in a substrate. At least a first sacrificial layer and a second sacrificial layer are respectively formed over the first source/drain region and the second source/drain region. A spacer layer is formed on at least a top surface of the substrate and around sides of the first sacrificial layer and the second sacrificial layer. The spacer layer includes an electrical-isolating material. The first sacrificial layer and a second sacrificial layer are removed to form a first open trench and a second open trench. The first open trench and the second open trench are filled with metal contact material to form a first metal contact and a second metal contact electrically isolated from each other by the spacer layer.

Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of cooling the polyester sheet, pushing up each device chip through the polyester sheet, and then picking up each device chip from the polyester sheet.

Abstract: Structures that include semiconductor fins and methods for forming a structure that includes semiconductor fins. A first fin comprised of n-type semiconductor material and a second fin comprised of p-type semiconductor material are formed. A conductive strap is formed that couples an end of the first fin with an end of the second fin.

Abstract: A method includes forming a transistor over a substrate; forming a conductive structure over the substrate, such that a first end of the conductive structure is electrically coupled to a gate of the transistor, and a second end of the conductive structure is electrically coupled to the substrate; applying biases to the gate of the transistor and source/drain structures of the transistor; determining whether the first end and the second end of the conductive structure are electrically connected; generating, based on the determination, a first result indicating that the first end and the second end of the conductive structure are electrically connected; and qualifiying the conductive structure as an antenna in response to the first result.

Abstract: A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; and a first fin stub on the substrate, wherein the first fin stub connects a first end of the first active fin and a first end of the second active fin, wherein the fin stub is lower than both the first and the second active fins in height, wherein from a top view the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor fin over a substrate. A fin spacer is formed on a sidewall of the semiconductor fin. An e-beam treatment is performed on the fin spacer. An epitaxial structure is formed over the semiconductor fin. The epitaxial structure is in contact with the e-beam treated fin spacer.

Abstract: This disclosure relates to a method of fabricating semiconductor devices with a gate-to-gate spacing that is wider than a minimum gate-to-gate spacing and the resulting semiconductor devices. The method includes forming gate structures over an active structure, the gate structures including a first gate structure, a second gate structure, and a third gate structure. The second gate structure is between the first and third gate structures. A plurality of epitaxial structures are formed adjacent to the gate structures, wherein the second gate structure separates two epitaxial structures and the two epitaxial structures are between the first and third gate structures. The second gate structure is removed. A conductive region is formed to connect the epitaxial structures between the first and third gate structures.

Abstract: Examples of an integrated circuit and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a substrate that includes: a plurality of fins extending above a remainder of the substrate; a first region that includes a first fence region that contains a first subset of the plurality of fins; and a second region that includes a second fence region that contains a second subset of the plurality of fins. The first region has a first performance characteristic, and the second region has a second performance characteristic that is different from the first. Based on the first performance characteristic, the first subset of the plurality of fins is recessed to a first height, and based on the second performance characteristic, the second subset of the plurality of fins is recessed to a second height that is less than the first height.

Abstract: Semiconductor structures and methods of making the same. The semiconductor structures including at least two vertically stacked nanosheet devices. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (HNS devices) that are stacked vertically, on top of each other, relative to a top surface of a substrate. The plurality of HNS devices including a first HNS device and a second HNS device that each have source and drain structures.

Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.

Abstract: A semiconductor device includes a first channel region disposed over a substrate, a first source region and a first drain region disposed over the substrate and connected to the first channel region such that the first channel region is disposed between the first source region and the first drain region, a gate dielectric layer disposed on and wrapping the first channel region, a gate electrode layer disposed on the gate dielectric layer and wrapping the first channel region, and a second source region and a second drain region disposed over the substrate and below the first source region and the first drain region, respectively. The second source region and the second drain region are in contact with the gate dielectric layer. A lattice constant of the first source region and the first drain region is different from a lattice constant of the second source region and the second drain region.

Abstract: There is provided a method of forming a semiconductor film, including: a first process of supplying a first semiconductor raw material gas onto a substrate having recesses formed therein to form a first semiconductor film in each of the recesses, each of the recesses being covered with an insulating film; a second process of supplying a halogen-containing etching gas onto the substrate to etch the first semiconductor film while exposing a surface of the insulating film in an upper portion of an inner wall of each of the recesses and leaving the first semiconductor film formed on a bottom surface of each of the recesses; and a third process of simultaneously supplying a halogen-containing semiconductor gas and a semiconductor hydride gas onto the substrate to form a second semiconductor film on the first semiconductor film formed on the bottom surface of each of the recesses.

Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.

Abstract: The present invention provides a thermal hardware-based data security device that is capable of physically, hardware-wise, and permanently erasing data stored in a memory and of enabling a storage device to be reused, and a method thereof. The thermal hardware-based data security device includes: a memory chip capable of storing data; a heater module which supplies heat to permanently erase the data stored in a memory cell within the memory chip; and a switch module which short-circuits the heater module between a power supply unit and a ground when switched on, and thus, controls the heater module to be operated.

Abstract: An example embodiment comprises a method for fabrication of a non-volatile memory (NVM) device. An isolation structure is formed in a substrate between first and second locations for first and second NVM cells. A common charge trapping layer is formed as a continuous structure over the substrate, where a first portion of the charge trapping layer is disposed directly over the isolation structure and second portions of the charge trapping layer are disposed directly over the first and second substrate locations. Nitrogen doping of the first portion of the charge trapping layer is performed, where after the nitrogen doping is performed the first portion of the charge trapping layer includes a higher nitrogen concentration than the second portions. The first and second NVM cells are then formed over the first and second substrate locations, where the first and second NVM cells include the second portions of the charge trapping layer.

Abstract: Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.

Abstract: A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of fins on a substrate. A fin end spacer is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. A gate electrode layer is formed on the insulating layer and wrapping around the each channel region. Sidewall spacers are formed on the gate electrode layer.

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 ?m2.

Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

Abstract: A method of forming a low-k layer includes forming a layer by providing a silicon source, a carbon source, an oxygen source, and a nitrogen source onto a substrate. The forming of the layer includes a plurality of main cycles, and each of the main cycles includes providing the silicon source, providing the carbon source, providing the oxygen source, and providing the nitrogen source, each of which is performed at least one time. Each of the main cycles includes sub-cycles in which the providing of the carbon source and the providing of the oxygen source are alternately performed.

Abstract: A method for fabricating a semiconductor device includes: forming a first conductive layer; forming a second conductive layer over the first conductive layer; forming a conductive line by etching the second conductive layer; etching a portion of the first conductive layer to form a plug head having the same critical dimension as the conductive line; forming a first spacer that covers the conductive line and the plug head; etching the remaining first conductive layer to form a plug body that is aligned with the first spacer, wherein the plug body have a greater critical dimension than the plug head; and forming a second spacer by performing a selective oxidation onto a side wall of the plug body.

Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.

Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming the electromagnetic waveguide. In an embodiment the electromagnetic waveguide includes a first spacer and a second spacer. In an embodiment, the first and second spacer each have a reentrant profile. The electromagnetic waveguide may also include a conductive body formed between in the first and second spacer, and a void formed within the conductive body. In an additional embodiment, the electromagnetic waveguide may include a first spacer and a second spacer. Additionally, the electromagnetic waveguide may include a first portion of a conductive body formed along sidewalls of the first and second spacer and a second portion of the conductive body formed between an upper portion of the first portion of the conductive body. In an embodiment, the first portion of the conductive body and the second portion of the conductive body define a void through the electromagnetic waveguide.

Abstract: The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a logic region disposed adjacent to the memory region. The memory region comprises a non-volatile memory (NVM) device having a control gate electrode and a select gate electrode disposed between two neighboring source/drain regions over a substrate. The control gate electrode and the select gate electrode comprise polysilicon. The logic region comprises a logic device including a metal gate electrode disposed between two neighboring source/drain regions over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer.

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.

Abstract: A radio frequency resistor element comprises a resistive polysilicon trace, an isolation component and a semiconductor substrate. The resistive polysilicon trace is located above the isolation component. The isolation component is laterally at least partially surrounded by a modified semiconductor region located above the semiconductor substrate and having a higher charge carrier recombination rate than the semiconductor substrate.

Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, and a first semiconductor layer over the substrate. At least a portion of the first semiconductor layer is surrounded by the isolation structure. The semiconductor device further includes a doped material layer between the isolation structure and the first semiconductor layer.

Abstract: Methods of forming an EDNMOS with polysilicon fingers between a gate and a nitride spacer and the resulting devices are provided. Embodiments include forming a polysilicon layer upon a GOX layer over a substrate; forming a gate and plurality of fingers and a gate and plurality of fingers through the polysilicon layer down the GOX layer; forming an oxide layer over the GOX layer and sidewalls of the gates and fingers; forming a nitride layer over the oxide layer; removing portions of the nitride and oxide layers down to the polysilicon and GOX layers to form nitride spacers; and forming S/D regions laterally separated in the substrate, each S/D region adjacent to a nitride spacer.

Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.

Abstract: An intelligent semiconductor device has a body region in which a channel is formed. The body region has a heterojunction of different semiconductor layers and a quantum well formed in a semiconductor layer in contact with a drain. The quantum well is configured to store holes generated in a depletion layer of the drain region and imitate a short-term memory, and to convert the short-term memory into a long-term memory by enabling holes to be injected into a charge storage layer when the holes stored in quantum well exceed a specific threshold value. It is possible to fabricate with a bulk semiconductor substrate and utilize the conventional CMOS technology.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first fin structure and a second fin structure disposed over the substrate. The semiconductor device structure includes a first gate stack disposed over the substrate and overlapping the first fin structure. The first gate stack includes a first work function layer, a first gate electrode, and a first hard mask layer, the first gate electrode is over the first work function layer, the first hard mask layer is over the first gate electrode, the first gate electrode has a first convex top surface protruding beyond a first top surface of the first work function layer. The semiconductor device structure includes a second gate stack disposed over the substrate and overlapping the second fin structure.

Abstract: An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.

Abstract: Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment.

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Abstract: A semiconductor device includes trench structures that extend from a first surface into a semiconductor body. The trench structures include a gate structure and a contact structure that extends through the gate structure, respectively. Transistor mesas are between the trench structures. Each transistor mesa includes a body zone forming a first pn junction with a drift structure and a second pn junction with a source zone. Diode regions directly adjoin one of the contact structures form a third pn junction with the drift structure, respectively.

Abstract: An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.

Abstract: A semiconductor device and a fabrication method are provided. The fabrication method includes providing a base substrate including a core region having a first gate structure formed thereon, and an edge region having a second gate structure formed thereon; forming a source/drain doped layer, in the core region of the base substrate on both sides of the first gate structure, and in the edge region of the base substrate on both sides of the second gate structure, respectively, the source/drain doped layer including first ions; and doping the second ions in the source/drain doped layer in the edge region, the second ions having a conductivity type opposite to the first ions.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

Abstract: A semiconductor power device formed in a semiconductor substrate that includes a plurality of trenches formed at a top portion of the semiconductor substrate. The trenches extend laterally across the semiconductor substrate along a longitudinal direction and each trench has a nonlinear portion thus the nonlinear portion has a trench sidewall perpendicular to the longitudinal direction of the trench. A plurality of trench bottom dopant regions are formed below the trench bottom surface. A sidewall dopant region is formed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.

Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.