Abstract: A bonded wafer 27 and a residual wafer 28 are placed in a state of being superimposed on each other on a susceptor 20 disposed in a heat treatment 10. A Bernoulli chuck 1 is moved to a wafer holding position 60 on a susceptor 20 by driving an arm 56, sucks the bonded wafer 27 positioned on the upper side and then moves to a bonded wafer recovery table 50? to recover the bonded wafer there. Then, similarly, the Bernoulli chuck 1 suction holds the residual wafer 28 at the wafer holding position 60 and then moves to a residual wafer recovery table 50? to recover the residual wafer there. With such a construction adopted, in a method for manufacturing a bonded wafer according to a so-called smart-cut method, not only is the separated bonded wafer recovered suppressing occurrence of a defect, deficiency and contamination, but there is also provided a method for manufacturing a bonded wafer capable of automation suitable for mass production.

Abstract: A method of fabricating a silicon-on-insulator structure having a silicon surface layer in a semiconductor workpiece, is carried out by maintaining the workpiece at an elevated temperature and producing an oxygen-containing plasma in the chamber while applying a bias to the workpiece and setting the bias to a level corresponding to an implant depth in the workpiece below the silicon surface layer to which oxygen atoms are to be implanted, whereby to form an oxygen-implanted layer in the workpiece having an oxygen concentration distribution generally centered at the implant depth and having a finite oxygen concentration in the silicon surface layer. The oxygen concentration in the silicon surface layer is then reduced to permit epitaxial silicon deposition.

Abstract: A method for producing a bonded wafer by the ion implantation delamination method includes at least a step of bonding a bond wafer having a micro bubble layer formed by gaseous ion implantation and a base wafer serving as a support substrate and a step of delaminating the bond wafer at the micro bubble layer as a border to form a thin film on the base wafer. After the delamination of the bond wafer, the bonded wafer is subjected to a heat treatment in an atmosphere of an inert gas, hydrogen or a mixed gas thereof, then the bonded wafer is subjected to thermal oxidation to form a thermal oxide film on the surface of the thin film, and then the thermal oxide film is removed to reduce thickness of the thin film.

Abstract: A method of fabricating a device having a desired non-planar surface or profile and device produced thereby are provided. A silicon wafer is first coated with silicon nitride, patterned, and DRIE to obtain the desired etch profile. Silicon pillars between trenches are then etched using an isotropic wet etch, resulting in a curved well. The wafer is then oxidized to ?2 ?m to smooth the surface of the well, and to protect the well from an ensuing planarization process. The nitride is then selectively removed, and the wafer surface is planarized by removing the Si left in the field regions using either a maskless DRIE or CMP. Finally, the oxide is etched away to produce a wafer with a curved surface.

Abstract: A semiconductor wafer (70) that includes a support body (72), at least one thin die (20, 60), and a plurality of tethers (78, 178). The support body (72) is made of a semiconductor material. The thin die (20, 60) has a circuit (21) formed thereon and has an outer perimeter (74) defined by an open trench (76). The open trench (76) separates the thin die (20, 60) from the support body (72). The tethers (78, 178) extend across the open trench (76) and between the support body (72) and the thin die (20, 60). A method of making a thin die (20, 60) on a wafer (70) where the wafer (70) has a support body (72), a topside (82) and a backside (90). A circuit (21) is formed on the topside (82) of the wafer (70).

Abstract: A method for treating a film of material, which can be defined on a substrate, e.g., silicon. The method includes providing a substrate comprising a cleaved surface, which had a porous silicon layer thereon. The substrate may have a distribution of hydrogen bearing particles defined from the cleaved surface to a region underlying said cleaved surface. The method also includes increasing a temperature of the cleaved surface to greater than about 1,000 Degrees Celsius while maintaining the cleaved surface in a etchant bearing environment to reduce a surface roughness value by about fifty percent and greater. Preferably, the value can be reduced by about eighty or ninety percent and greater, depending upon the embodiment.

Abstract: A method for fabricating silicon tiles and silicon tile targets has been provided, such as may be used in the sputter deposition of thin film transistor (TFT) silicon films. The method describes processes of cutting the tiles, beveling the tiles edges, etching the tiles to minimize residual damage caused by cutting the tiles, polishing the tiles to a specified flatness, and attaching the tiles to a backing plate. All these processes are performed with the aim of minimizing contamination and particle formations when the target is used for sputter deposition.

Abstract: A method for fabricating a vertical integrated circuit is disclosed. Integrated circuits are fabricated on a substrate with layers of predetermined weak and strong bond regions where deconstructed layers of integrated circuits are fabricated at or on the weak bond regions. The layers are then peeled and subsequently bonded to produce a vertical integrated circuit. An arbitrary number of layers can be bonded and stacked in to a separate vertical integrated circuit. Also disclosed are methods of creating edge interconnects and vias through the substrate to form interconnections between layers and devices thereon.

Abstract: In an integrated pressure sensor including a semiconductor substrate having a p type single crystal silicon substrate and an n type epitaxial layer of which a portion is etched by electrochemical etching to have a diaphragm, an impurity diffusion layer piercing the n type epitaxial layer at least defining the diaphragm is formed for isolation. An etching wire is formed on the surface of the n type epitaxial layer with insulation and the first end of the etching wire extends to the inside of the surface and connected to the n type epitaxial layer. The second opposite end extends to an edge of the semiconductor substrate. The etching wire does not cross the impurity layer inside the surface of the semiconductor substrate to prevent the etching wire from short-circuiting with the impurity diffusion layer during the electrochemical etching.

Abstract: A process of lapping a wafer includes the steps of relieving adhesive stress of an ultraviolet tap attached to a first side of the wafer by irradiation of ultraviolet light, maintaining a lapping jig at a usable temperature of the ultraviolet tape to cause a binder applied to the lapping jig to be melted, bonding the first side of the wafer to the lapping jig, and lapping the wafer.

Abstract: The invention provides for a method of manufacturing a stacked power chip resistor. The method includes adhering a first chip resistor to a second chip resistor with a glass encapsulant, connecting a first terminal of the first chip resistor to a first terminal of the second chip resistor with the first metal barrier, and connecting a second terminal on the first chip resistor to a second terminal of the second chip resistor with a second metal barrier.

Abstract: A method of fabricating substrates while minimizing loss of starting material of an ingot, wherein a layer is transferred onto a support. The technique includes forming a flat front face on a raw ingot of material, implanting atomic species through the front face to a controlled mean implantation depth to create a zone of weakness that defines a top layer of the ingot, bonding a support to the front face of the ingot, wherein the support has a surface area that is smaller than a surface area of the front face of the ingot, and detaching from the ingot at the zone of weakness that portion of the top layer that is bonded to the support to form the substrate.

Abstract: A semiconductor wafer is applied to a support disk via an intervening adhesive layer with the front side of the semiconductor wafer facing the adhesive layer, which is sensitive to a certain exterior factor for reducing its adhesive force; the semiconductor wafer is ground on the rear side; the wafer-and-support combination is applied to a dicing adhesive tape with the so ground rear side facing the dicing adhesive tape, which is surrounded and supported by the circumference by a dicing frame; the certain exterior factor is effected on the intervening adhesive layer to reduce its adhesive force; and the intervening adhesive layer and support disk are removed from the semiconductor wafer or chips without the possibility of damaging the same.

Abstract: A method of manufacturing a semiconductor substrate (7) includes the processes of: forming an insulation film (2) on a surface of a semiconductor substrate main body (1); forming an ion shield member (3) having a predetermined shape on the insulation film; implanting an ion into the semiconductor substrate main body from a side on which the insulation film is formed, to thereby form an ion implantation layer (1a, 1b); removing the ion shield member; laminating the insulation film and a support substrate (5) onto each other; and separating the semiconductor substrate main body from the support substrate at a portion of the ion implantation layer.

Abstract: A method of fabricating devices incorporating microelectromechanical systems (MEMS) using UV curable tapes includes providing a silicon substrate 12 with a MEMS layer 14 arranged on one side of the substrate 12. A first UV curable tape 22 is applied to the MEMS layer 14. At least one operation is performed on the substrate 14 via an opposed side of the substrate 14. A second UV curable tape 32 is applied to the opposed side of the substrate 14 and the first tape 22 is removed by exposing it to UV light. At least one operation is performed on the MEMS layer to form individual MEMS chips which are able to be removed individually from the second UV tape 32 by localised exposure of the tape 32 to UV light.

Abstract: A method for producing an SOI wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating a wafer having an SOI layer at the micro bubble layer as a border, wherein, after the delamination step, the wafer having an SOI layer is subjected to a two-stage heat treatment in an atmosphere containing hydrogen or argon utilizing a rapid heating/rapid cooling apparatus (RTA) and a batch processing type furnace. Preferably, the heat treatment by the RTA apparatus is performed first. Surface roughness of an SOI layer surface delaminated by the hydrogen ion delamination method is improved over the range from short period to long period, and SOI wafers free from generation of pits due to COPs in SOI layers are efficiently produced with high throughput.

Abstract: A memory IC includes a first substrate (substrate on the transfer destination side), and memory cell arrays deposited on the first substrate. The memory cell arrays are deposited from the bottom up by a method for transferring a thin film configuration. The transferring method includes the steps of forming a thin film device layer (memory cell array) on a second substrate with a separable layer therebetween, and irradiating the separable layer with light to cause a separation in the separable layer and/or at an interface so that the thin film device layer on the second substrate is transferred to the first substrate.

Abstract: In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments, one conductive layer provides an electromagnetic shield that shields the substrate from AC signals carried by a contact pad made from another conductive layer on a backside of the substrate. The conductive layers can also be used to form capacitor/rectifier networks. Manufacturing methods also provided.

Abstract: The present invention comprises the steps of forming a bump metal film as a pattern having an opening portion on an area of a seed metal film that corresponds to a connecting pad of a semiconductor substrate, forming a through hole by etching the seed metal film, the connecting pad, and the semiconductor substrate located under the opening portion of the bump metal film while using the bump metal film as a mask, grinding a back surface of the semiconductor substrate, forming an insulating film on a side surface of the through hole, forming a through wiring in the through hole by an electroplating, and forming a metal bump by etching the seed metal film.

Abstract: The present invention provides a method for producing a bonded dielectric separation wafer in which an auto-alignment can be carried out with reference to the orientation flat of a supporting substrate wafer after the wafer bonding step, and also an apparatus to be used for bonding wafers. When wafers are placed one upon another, the silicon wafers 10, 20 are irradiated with transmission light in order to capture the transmission images thereof. The positions of the pattern of dielectric isolation grooves 13 in the silicon wafer 10 and the orientation flat 20a of the silicon wafer 20 are determined from the images and the bonding position of the wafers 10, 20 is determined based on the determined positions. Auto-alignment of the bonded dielectric separation wafer can thereby be carried out with reference to the orientation flat 20a of the silicon wafer 20 after the wafer bonding step.

Abstract: A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.

Abstract: Substrates suitable to manufacture and products of a thin film semiconductor device are provide, by at first preparing a manufacturing substrate having a characteristic of being capable of enduring a process for forming a thin film transistor and a product substrate having a characteristic of being suitable to direct mounting of the thin film transistor in a preparatory step, then applying a bonding step to bond the manufacturing substrate to the product substrate for supporting the product substrate at the back, successively applying a formation step to form at least a thin film transistor to the surface of the product substrate in a state reinforced with the manufacturing substrate and, finally, applying a separation step to separate the manufacturing substrate after use from the product substrate.

Abstract: A method for manufacturing vertical GaN light emitting diodes starts by forming a light emitting structure on a sapphire substrate, said light emitting structure including a first conductive GaN clad layer, an active layer and a second conductive GaN clad layer. The light emitting structure is divided into plural units so that the first conductive GaN clad layer of a thickness of at least approximately 100 Å remains. A conductive substrate is attached to the divided upper surface of the light emitting structures using a conductive adhesive layer. A lower surface of the sapphire substrate is irradiated by laser beam so that the sapphire substrate is removed from the unit light emitting structures. First and second contacts are formed respectively on the surfaces of the first conductive clad layer and the conductive substrate. Finally, the resulting structure is cut into plural unit light emitting diodes.

Abstract: A silicon on insulator substrate apparatus for fabricating an active-matrix liquid crystal display is described herein. The silicon on insulator substrate may include a handle substrate and a plurality of crystalline silicon donor portions bonded to the handle substrate. The crystalline silicon donor portions may be bonded to the handle substrate by providing a plurality of donor substrates and forming a separation layer within each donor substrate. The donor substrates may be arranged across a surface of the handle substrate and subsequently bonded to the handle substrate. The donor substrates may then be cleaved at their respective separation layers and removed from the handle substrate, thereby leaving a donor portion of each donor substrate attached the handle substrate.

Abstract: A method for manufacturing a semiconductor device which enables favorable back-surface grinding of a semiconductor substrate with preventing a warp in the substrate, thereby manufacturing a thickness-reduced semiconductor device. A projection electrode is formed on a surface of a wafer. A resin layer is formed on the wafer surface to a thickness to bury a top of the projection electrode. A cut groove is formed in the resin layer along a scribe line formed on the wafer. Thereafter, grinding is made on a back surface of the wafer by the use of a grinder or the like. A surface portion of the resin layer is removed by etching or the like, to expose the top of the projection electrode. The wafer is cut along the cut groove to obtain individual semiconductor chip pieces.

Abstract: Substrates suitable to manufacture and products of a thin film semiconductor device are provide, by at first preparing a manufacturing substrate having a characteristic of being capable of enduring a process for forming a thin film transistor and a product substrate having a characteristic of being suitable to direct mounting of the thin film transistor in a preparatory step, then applying a bonding step to bond the manufacturing substrate to the product substrate for supporting the product substrate at the back, successively applying a formation step to form at least a thin film transistor to the surface of the product substrate in a state reinforced with the manufacturing substrate and, finally, applying a separation step to separate the manufacturing substrate after use from the product substrate.

Abstract: The invention relates to a process for making a thin film starting from a substrate (1) of a solid material with a plane face (2) comprising: the implantation of gaseous compounds in the substrate (1) to make a layer of micro-cavities (4) at a depth from the said plane face (2) corresponding to the thickness of the required thin film, the gaseous compounds being implanted under conditions that could weaken the substrate at the layer of micro-cavities, partial or total separation of the thin film from the rest of the substrate (1), this separation comprising a step in which thermal energy is added and pressure is applied to the said plane face (2).

Abstract: The invention relates to a method of producing a thin layer of semiconductor material including: a step of implanting ions through a flat face (2) of a semiconductor wafer in order to create a layer of microcavities, the ion dose being within a specific range in order to avoid the formation of blisters on the flat face, a thermal treatment step in order to achieve coalescence of the microcavities a possibly, a step of creating at least one electronic component (5) in the thin layer (6), a separation step of separating the thin layer (6) from the rest (7) of the wafer.

Abstract: On a sapphire base (701), a GaN layer (702) and a substrate separating layer (703) are sequentially deposited, and the GaN layer (702) and the substrate separating layer (703) are processed to have a plurality of ridge stripes (702a) and recess portions (702b). Subsequently, a GaN based semiconductor layer (706) is grown on a C surface (703c) of the substrate separating layer (703) exposed on top of ridge stripes (702a) as seed crystal. The C surface (703c) of the substrate separating layer (703) is irradiated with a laser beam (802) to remove the substrate separating layer (703), thereby separating the GaN based semiconductor layer (706) from the sapphire base (701).

Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.

Abstract: A structure and method of formation. The substrate has front and back surfaces on opposite sides of the substrate. The substrate has a backside portion extending from the back surface to a second depth into the substrate as measured from the front surface. At least one via is formed in the substrate and extends from the front surface to a via depth into the substrate. The via depth is specific to each via. The via depth of each via is less than an initial thickness of the substrate. The second depth does not exceed the minimum via depth of the via depths. Organic material (e.g., photoresist) is inserted into each via. The organic material is subsequently covered with a tape, followed by removal of the backside portion of the substrate. The tape is subsequently removed from the organic material, followed by removal of the organic material from each via.

Abstract: A method for manufacturing integrated circuits uses an atmospheric magnetic mirror plasma etching apparatus to thin a semiconductor wafer. In addition the process may, while thinning, both segregate and expose through-die vias for an integrated circuit chip. To segregate, the wafer may be partially diced. Then, the wafer may be tape laminated. Next, the backside of the wafer may be etched. As the backside material is removed, the partial dicing and through-die vias may be exposed. As such, the method reduced handling steps and increases yield. Furthermore, the method may be used in association with wafer level processing and flip chip with bump manufacturing.

Abstract: Methods for thinning wafer-to-wafer vertical stacks in the fabrication of stacked microelectronic devices. The methods include physically removing unsupported portions of a wafer to be thinned in the vertical stack. The removal of the unsupported portions substantially eliminates potential cracking and chipping of the wafer, which can occur during the thinning process when the unsupported portions exist.

Abstract: A new silicon structure is provided. Under a first embodiment of the invention, a first silicon substrate having a <100> crystallographic orientation is bonded to the surface of a second silicon substrate having a <110> crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are aligned with each other. Under a first embodiment of the invention, a first silicon substrate having a <100> crystallographic orientation is bonded to the surface of a second silicon substrate having a <110> crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are not aligned with each other.

Abstract: A method of treating a silicon surface of a substrate that includes heating the substrate in a process chamber to a temperature, exposing a first area adjacent to the silicon surface to a first gas mixture comprising an etchant, a silicon source gas, and a carrier, exposing a second area adjacent to the silicon surface to a second gas mixture, wherein the second gas mixture is different from the first gas mixture.

Abstract: Chips C which have already been diced are attached to a ring frame F using an adhesive sheet, and a protective sheet S1 is attached to a circuit pattern surface of the chips C. The chips C, along with a ring frame F, are held in place on a table 27 of a protective sheet peeling apparatus 20. A supply portion for an adhesive tape T is disposed in the vicinity of a table 24, and the supplied adhesive tape T is attached to the protective sheet S1. When the protective sheet S1 is peeled from the circuit pattern surface, peeling starts from corner portions of the chips C or opposing corner positions by pulling the adhesive tape T.

Abstract: A method for fabricating silicon tiles and silicon tile targets has been provided, such as may be used in the sputter deposition of thin film transistor (TFT) silicon films. The method describes processes of cutting the tiles, beveling the tiles edges, etching the tiles to minimize residual damage caused by cutting the tiles, polishing the tiles to a specified flatness, and attaching the tiles to a backing plate. All these processes are performed with the aim of minimizing contamination and particle formations when the target is used for sputter deposition.

Abstract: A process for transfer of at least one thin film of solid material delimited in an initial substrate. The process includes a step in which a layer of inclusions is formed in the initial substrate at a depth corresponding to the required thickness of the thin film. These inclusions are designed to form traps for gaseous compounds which subsequently are implanted. In a subsequent step gaseous compounds are implanted in a manner to convey the gaseous compounds into the layer of inclusions. The dose of implanted gaseous compounds is made sufficient to cause the formation of micro-cavities to form a fracture plane along which the thin film can be separated from the remainder of the substrate.

Abstract: To accomplish both of higher performance of a crystal and lower cost in a semiconductor member, and to produce a solar cell having a high efficiency and a flexible shape at low cost, the semiconductor member is produced by the following steps, (a) forming a porous layer in the surface region of a substrate, (b) immersing the porous layer into a melting solution in which elements for forming a semiconductor layer to be grown is dissolved, under a reducing atmosphere at a high temperature, to grow a crystal semiconductor layer on the surface of the porous layer, (c) bonding another substrate onto the surface of the substrate on which the porous layer and the semiconductor layer are formed and (d) separating the substrate from the another substrate at the porous layer.

Abstract: A bump is formed at a predetermined position on a surface of a semiconductor wafer and a sealing resin is formed so as to cover the surface and to make a surface of the bump exposed. Then, a reinforcing plate is bonded to the sealing resin and the exposed surface of the bump through an adhesive, and a rear portion of the semiconductor wafer is ground using a grind stone or removed by wet etching. Then, the rear surface of the thinned semiconductor wafer is covered with another sealing resin.

Abstract: A first semiconductor layer is formed on a mother substrate, and the mother substrate is irradiated with irradiation light from a surface opposite to the first semiconductor layer, so that a thermally decomposed layer formed by thermally decomposing the first semiconductor layer between the first semiconductor layer and the mother substrate. Then, a second semiconductor layer including an active layer is formed on the first semiconductor layer in which the thermally decomposed layer is formed.

Abstract: A method of coupling a single crystal semiconductor layer to a support substrate. Thinning the single crystal layer. Introducing an integrated circuit into the single crystal layer. And removing the thinned single crystal layer with the integrated circuit from the support substrate.

Abstract: A method of relieving surface stress on a thin wafer by removing a small portion of the wafer substrate, the substrate being removed by applying a solution of KOH to the wafer while the wafer spins.

Abstract: A method of separating two layers of material from one another in such a way that the two separated layers of material are essentially fully preserved. An interface between the two layers of material at which the layers of material are to be separated, or a region in the vicinity of the interface, is exposed to electromagnetic radiation through one of the two layers of material. The electromagnetic radiation is absorbed at the interface or in the region in the vicinity of the interface and the absorbed radiation energy induces a decomposition of material at the interface.

Abstract: Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication there is first provided a first semiconductor substrate. There is then formed over the first semiconductor substrate at least one microelectronic device to form from the first semiconductor substrate a partially fabricated semiconductor integrated circuit microelectronic fabrication. Within the method there is also provided a second substrate. There is also formed over the second substrate, in inverted order, a dielectric isolated metallization pattern intended to mate with the partially fabricated semiconductor integrated circuit microelectronic fabrication.

Abstract: A method for manufacturing a semiconductor device is capable of controlling amounts of protrusion of penetration electrodes (5) from a rear surface of a semiconductor substrate (4) in a easy and accurate manner. Recesses (7) are formed in a substrate proper (6) that has a semiconductor circuit (2) formed on one surface thereof, and an insulation film (8) is formed on an inner wall surface of each of the recesses (7). A conductive material is filled into the recesses (7) through the insulation films (8) to form embedded electrodes (15) that constitute the penetration electrodes (5). A rear side of the substrate proper (6) is re moved until one end face of each of the embedded electrodes (15) is exposed, thereby to form the penetration electrodes (5). The rear surface of the substrate proper (6) is anodized to form an anodic oxide film (9), which is then removed by etching to form the semiconductor substrate (4).

Abstract: Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.

Abstract: Disclosed herein is a pressure sensitive adhesive sheet for fixing a semiconductor wafer during semiconductor wafer processing in vacuum, comprising a substrate and, superimposed on one side or both sides thereof, a layer of ultraviolet curable pressure sensitive adhesive composition comprising an ultraviolet curable copolymer having ultraviolet polymerizable groups as side chains and a phosphorous photopolymerization initiator. The pressure sensitive adhesive sheet for semiconductor wafer processing, even in the processing of a semiconductor wafer in vacuum, is free from generating gases from the pressure sensitive adhesive sheet, thereby avoiding wafer deformation attributed to evaporated gas components and adhesive transfer caused thereby.

Abstract: To provide a semiconductor device capable of corresponding to an applied bending stress by flexibly changing its shape, and to provide a semiconductor device module, a manufacturing method of the semiconductor device, and a manufacturing method of the semiconductor device module. In a silicon substrate whose front surface is provided with an element forming layer having an element forming region where a semiconductor element is formed, a groove is formed in a portion of the rear surface of the silicon substrate corresponding to a region of the element forming layer where a semiconductor element is not formed.

Abstract: In a method for reclaiming a delaminated wafer produced as a by-product in the production of bonded wafer by the ion implantation and delamination method, at least ion-implanted layer on a chamfered portion of the delaminated wafer is removed, and then a surface of the wafer is polished. Specifically, at least a chamfered portion of the delaminated wafer is subjected to an etching treatment and/or processing by chamfering, and then a surface of the wafer is polished. Alternatively, the delaminated wafer is subjected to a heat treatment, and then polished. There are provided a method for reclaiming a delaminated wafer, which provides a reclaimed wafer of high quality that does not generate particles even when it is subjected to a heat treatment with good yield, and such a reclaimed wafer.